1. Introduction
The use of temperature sensors is widespread in system on chip (SoC) design, where they serve a variety of purposes, such as detecting environmental temperature, monitoring hot spots on the chip, and aiding other circuits [1]-[7]. Thus, recent VLSI systems typically require multiple temperature sensors. In particular, for applications such as hot spot thermal detection, a small sensor footprint is essential to ensure proximity to the hot spot. Besides, such temperature sensors are typically powered by digital power supplies, which often exhibit significant voltage fluctuations. Consequently, temperature sensors for SoC design must be low power, occupy minimal silicon area, and immune to power supply voltage fluctuations. Additionally, low calibration costs are desirable. A temperature sensor with no calibration or one-point calibration near room temperature is preferable to those requiring two-point calibration or one-point calibration at high temperatures, which can be costly in non-room temperature environments.
While conventional temperature sensors based on BJT or resistors offer excellent precision, they tend to occupy significant chip area and consume high levels of power, making them less desirable for SoC design [8]-[17]. Furthermore, reducing their area and power consumption through process upgrades is challenging. On the other hand, MOSFET-based temperature sensors are compatible with digital circuits process and can improve their performance further with process upgrades. However, they are susceptible to process variation which often require an expensive two-point calibration scheme to achieve the desired accuracy. Besides, their performance in supply sensitivity tend to be poor [18]-[31].
This letter presents a compact, low-power temperature sensor front-end based solely on MOSFETs, which is well-suited for SoC designs. To address output voltage variation across chips, a differential voltage readout scheme is employed, and a dynamic element matching (DEM) circuit is used to further reduce mismatch of MOSFETs. A real-time voltage calibration (RVC) method is proposed to enhance performance in supply sensitivity of the sensor. The sensor is self-referenced, eliminating the need for an external reference source and minimizing system power consumption.
2. Operation principle
Fig. 1 presents the structural diagram of the proposed temperature sensor front-end. The middle part of Fig. 1. is a compact MOSFET-based complementary to absolute temperature (CTAT) voltage generator circuit, which produces a CTAT voltage denoted as \(V_{CTAT}\). On the right-hand side of Fig. 1, a two-stage proportional to absolute temperature (PTAT) voltage bias circuit employs \(V_{CTAT}\) as an input voltage and introduces a PTAT component to the original voltage. By adjusting the W/L ratios of MOSFETs in the Fig. 1, the resulting output voltage, \(V_{ZTC}\), remains independent of temperature changes, serving three functions:
- The temperature sensor readout voltage, denoted as \(V_{DIFF}\), represents the differential voltage between \(V_{ZTC}\) and \(V_{CTAT}\), exhibiting PTAT characteristics.
- The voltage value of \(V_{ZTC}\) is employed for RVC.
- \(V_{ZTC}\) provides reference voltage for bias circuits.
2.1 Main temperature sensing element
The proposed temperature sensor employs a two-stage PTAT voltage bias circuit located on the left-hand side of Fig. 2 as the main temperature sensing element. Each stage adds a PTAT component to the input node, resulting in the differential voltage between the input and output, \(V_{GG7,8}\), which can be expressed as:
\[\begin{align} \begin{split} V_{GG7,8} &=V_{GS8}-V_{GS7} \end{split} \tag{1} \end{align}\] |
Where \(V_{GS7}\) and \(V_{GS8}\) are the voltages between the gate and source of \(M_{7}\) and \(M_{8}\). These MOSFETs operate in the subthreshold region, which provides them with linear temperature characteristics and low power consumption. The drain current of MOSFETs in the subthreshold region can be expressed as:
\[\begin{align} \begin{split} I_D&=\mu C_{ox}^{'}\frac{W}{L}(n-1)V_{t}^{2}\cdot exp\left(\frac{V_{GS}-V_{TH}+{\lambda}V_{DS}}{nV_{t}}\right) \end{split} \tag{2} \end{align}\] |
Where \(\mu\) is carrier mobility, \(C_{ox}^{'}\) is sheet oxide-capacitance density, \(W\) and \(L\) are the width and length of MOS, \(V_{TH}\) is threshold voltage, \(\lambda\) is drain-induced barrier lowering (DIBL) effect coefficient, \(V_{DS}\) is drain-source voltage of MOS, \(n\) is sub-threshold slope, \(V_t\) is the thermal voltage given by:
\[\begin{align} \begin{split} V_t=\frac{kT}{q} \end{split} \tag{3} \end{align}\] |
Where \(k\) is the Boltzmann constant and \(q\) is the electron charge. Based on equations (2) and (3), \(V_{GS}\) can be derived as:
\[\begin{align} \begin{split} V_{GS}&=ln\left[\frac{I_D}{\mu C_{ox}^{'} \frac{W}{L}(n-1) V_t^2}\right]\cdot nV_t + V_{TH} - {\lambda}V_{DS} \end{split} \tag{4} \end{align}\] |
By substitute this into the expression for \(V_{GG7,8}\) and setting the \(W/L\) ratios of \(M_7\), \(M_8\), \(M_{9}\) and \(M_{10}\) to \(K_7\), \(K_8\), \(K_{9}\) and \(K_{10}\), respectively, the \(V_{GG7,8}\) of the PTAT voltage bias circuit can be further derived:
\[\begin{align} \begin{split} V_{GG7,8}&=n\frac{k}{q}ln\left(\frac{K_{7}K_{10}}{K_{8}K_{9}}\right)\cdot T + {\lambda}{\Delta}V_{DS7,8} \end{split} \tag{5} \end{align}\] |
Although \(V_{GG7,8}\) is linearly related to temperature according to equation (5), achieving a high slope of the temperature curve using only one stage of the PTAT voltage bias circuit would require a relatively large amount of circuit area due to the logarithmic relationship between the coefficients of \(T\) and \((K_{8}K_{11})/(K_{9}K_{10})\). To address this issue, the proposed design incorporates a two-stage PTAT voltage bias circuit to further reduce circuit area and increase the slope of the output temperature slope.
2.2 Dynamic device matching
The proposed sensor’s accuracy is improved by introducing a DEM mechanism to the PTAT voltage bias circuit. As depicted in the left-hand side of Fig. 2, each red block comprising \(M_7\) and \(M_8\), \(M_{9}\) and \(M_{10}\) is designed as multiple identical MOSFETs presented in the right-hand side of Fig. 2, and they can interchange with each other through analog switches. When DEM is activated, the green and blue MOSFETs will swap with each other after each differential voltage measurement. One round of MOSFETs exchange represents a DEM cycle, and the final output voltage is the average voltage of each measurement result in one DEM cycle, which can be expressed as:
\[\begin{align} \begin{split} V_{out}&=\frac{\sum\limits_{i=1}^{N}V_{outN}}{N} \end{split} \tag{6} \end{align}\] |
The DEM scheme can significantly suppress measurement error caused by mismatch. The theoretical analysis of the impact of the mismatch between \(M_7\) and \(M_8\) is as follows. To simplify the analysis, the DIBL effect is ignored, and it is assumed that \(M_9\) and \(M_{10}\) in Fig. 2 have the same size and no mismatch. The ratio of M7 and M8 is 1:2, they are composed of three identical MOSFETs, and there is mismatch between them, resulting in \(K_7\):\(K_8\) = 1+\({\delta}\):2. According to (5), the \(V_{GG}\) value without mismatch (\(V_{GG1}\)) can be obtained as:
\[\begin{align} \begin{split} V_{GG1}&=n\frac{k}{q}ln\left(\frac{1}{2}\right)\cdot T \end{split} \tag{7} \end{align}\] |
The \(V_{GG}\) value considering mismatch before DEM (\(V_{GG2}\)) is:
\[\begin{align} \begin{split} V_{GG2}&=n\frac{k}{q}ln\left(\frac{1+{\delta}}{2}\right)\cdot T \end{split} \tag{8} \end{align}\] |
After enabling the DEM, the \(V_{GG}\) value (\(V_{GG3}\)) can be expressed as:
\[\begin{align} \begin{split} V_{GG3}&=\frac{1}{3}n\frac{k}{q}ln\left(\frac{1+{\delta}}{2(2+{\delta})^2}\right)\cdot T \end{split} \tag{9} \end{align}\] |
Assuming the mismatch error value \(\delta\) is 0.01, the ratio of \(V_{GG2}\) to \(V_{GG1}\) and \(V_{GG3}\) to \(V_{GG1}\) are 98.56% and 100.001%, respectively. The analysis result shows the introduction of DEM greatly suppresses the mismatch error between \(M_7\) and \(M_8\), and the mismatch error between \(M_9\) and \(M_{10}\) can also be calculated though the same method.
2.3 Real-time voltage calibration
\(M_4\) is a diode-connected high-threshold voltage MOSFET operating in the subthreshold region. \(V_{CTAT}\) is the gate-source voltage of \(M_4\), which can be represented by (4). The threshold voltage \(V_{TH}\) exhibits an CTAT characteristics [7]. Since the value of \(V_{TH}\) is much higher than the first term in (4) by adjusting the parameters of \(M_4\), \(V_{CTAT}\) exhibits CTAT characteristics. \(V_{ZTC}\) can be expressed as:
\[\begin{align} \begin{split} V_{ZTC}&= V_{CTAT}+V_{GG7,8}+V_{GG12,13} \end{split} \tag{10} \end{align}\] |
Where \(V_{CTAT}\) can be derived by (4), \(V_{GG7,8}\) and \(V_{GG12,13}\) can be derived by (5). Since the first term in (4) and (5) is PTAT, and the second term in (4) is CTAT, \(V_{ZTC}\) can be independent of temperature by adjusting W/L value of MOSFETs, which can be expressed as:
\[\begin{align} \begin{split} V_{ZTC}&= A - {\lambda}(V_{DS4}-{\Delta}V_{DS7,8}-{\Delta}V_{DS12,13}) \end{split} \tag{11} \end{align}\] |
Where A include the threshold voltage of \(M_4\) with CTAT characteristics and the PTAT characteristics term in (4) and (5). By adjusting the MOSFETs parameters appropriately, A can be made independent of temperature variations. Typically, the value of \(V_{DS}\) is linearly related to the power supply voltage [18]. The equation (11) can be further written as:
\[\begin{align} \begin{split} V_{ZTC}&= A - {\lambda}({\alpha}-{\beta}-{\gamma})VDD \end{split} \tag{12} \end{align}\] |
Where \({\alpha}VDD\), \({\beta}VDD\) and \({\gamma}VDD\) represent \(V_{DS4}\), \({\Delta}V_{DS7,8}\) and \({\Delta}V_{DS12,13}\), respectively.
\(V_{ZTC}\) can be utilized for RVC as follows: The chip is powered at 1.2 V as standard supply voltage in a 30℃ environment for one point calibration. During this process, in addition to recording the differential readout voltage for temperature calibration, the value of \(V_{ZTC}\) at standard supply voltage, \(V_{ZTC1v2}\), is also recorded. According to equation (12), \(V_{ZTC}\) is constant with temperature but increases linearly with the supply voltage.
In a actual measurement, both \(V_{ZTC}\) and \(V_{CTAT}\) voltages are collected. The difference between the measured value of \(V_{ZTC}\) and \(V_{ZTC1v2}\) can be obtained by subtracting them:
\[\begin{align} \begin{split} {\Delta}V_{ZTC}=V_{ZTC} - V_{ZTC1v2}&= -{\lambda}({\alpha}-{\beta}-{\gamma}){\Delta}VDD \end{split} \tag{13} \end{align}\] |
The difference between the measured \(V_{DIFF}\) and \(V_{DIFF1v2}\) witch represent differential readout voltage at the 1.2 V standard supply voltage can be expressed as:
\[\begin{align} \begin{split} V_{DIFF} - V_{DIFF1v2}&= {\lambda}({\beta}+{\gamma}){\Delta}VDD \end{split} \tag{14} \end{align}\] |
Substituting (13) into (14), \(V_{DIFF1v2}\) can be represent as following:
\[\begin{align} \begin{split} V_{DIFF1v2}&= V_{DIFF} + \frac{{\beta}+{\gamma}}{{\alpha}-{\beta}-{\gamma}}\cdot{\Delta}V_{ZTC} \end{split} \tag{15} \end{align}\] |
Since \(\alpha\), \(\beta\) and \(\gamma\) are all constants, the ratio of \(({\beta}+{\gamma})\) and \(({\alpha}-{\beta}-{\gamma})\) can be obtained through measurements during calibration. Once the value of \({\Delta}V_{ZTC}\) and \(V_{DIFF}\) is obtained, the \(V_{DIFF1v2}\) value at the standard supply voltage can be calculated through (15), regardless of the current power supply voltage. \(V_{DIFF1v2}\) is used as calibrated output voltage value, thus achieving voltage calibration.
2.4 Self bias circuit
The reference current source is generated by \(M_1\), which is a big length high-threshold voltage MOSFET transistor that produces nA-level current under the bias of \(V_{ZTC}\).
Although the current of \(M_1\) does vary with temperature and supply voltage, as shown in (5), the voltage bias generated by the PTAT Voltage Bias circuit (i.e., \(V_{DIFF}\)) is independent of supply current. And the gate-source voltage of \(M_4\), \(V_{GS4}\) (i.e., \(V_{CTAT}\)), is determined by (4), where the term with \(I_D\) is much smaller than \(V_{TH4}\), which makes \(V_{CTAT}\) less affected by \(I_D\).
3. Simulation result and circuit implementation
The readout voltage of the proposed sensor \(V_{DIFF}\) is obtained from the differential voltage between \(V_{CTAT}\) and \(V_{ZTC}\). This differential readout scheme effectively eliminates the readout voltage variation across chips. Simulation results of \(V_{CTAT}\), \(V_{ZTC}\), and their differential voltage \(V_{DIFF}\) at three different process corners are presented in Fig. 3. It is observed that the single-ended output voltage \(V_{CTAT}\) and \(V_{ZTC}\) in Fig. 3(a) show significant variation across different corners, making it impossible to accurately convert the voltage to a temperature value. On the other hand, the differential readout voltage \(V_{DIFF}\) in Fig. 3(b) maintains good consistency across process corners. The temperature error, converted by \(V_{DIFF}\) without any calibration, is below \(\pm\)1.3℃ across these three corners. The voltage variation in Fig. 3(a) is mainly caused by the susceptibility of MOSFET parameters, such as threshold voltage, to process variation. However, according to equation (5), \(V_{DIFF}\) is almost only related to the W/L ratios of different MOSFETs. The W/L ratios between nearby MOSFETs are relatively precise in CMOS process through careful placement, resulting in little impact on \(V_{DIFF}\) due to process variation.
Fig. 3 Simulation results of each output voltage at three different process corners. |
Fig. 4 shows the power supply sensitivity curves of the sensor after RVC at 1.1 V and 1.3 V supply voltages, with maximum power supply sensitivities of only 5.4℃/V and 3.7℃/V, respectively.
In SoC design, the temperature sensor front-end typically shares the analog-to-digital converter (ADC) integrated into the system. Thanks to the two-stage temperature sensing structure, the output temperature slope achieves 0.92 mV/℃ as shown in Fig. 3(b). This relatively high output temperature slope enables the utilization of state-of-the-art low-power ADCs [32] in VLSI systems, achieving a moderate temperature resolution. Fig. 5 displays the circuit diagram of the test chip. To evaluate the mismatch error and simulate a multiple temperature sensor node environment, eight sensors front-ends are incorporated in the circuit. These sensors are connected to an eight-channel multiplexer and an operational amplifier is used as a buffer stage, which is connected to the output port of the multiplexer. The differential output signal is buffered and then sent to an external ADC for measurement. The proposed sensor is manufactured through a 55 nm process, with a single sensor front-end area of only 840 \(\mu m^2\), as shown in Fig. 6.
4. Measurement results
A total of 16 temperature sensors were measured using an external differential ADC with a 16-bit resolution with a reference voltage of \(\pm\)2.5 V and a sample rate of 200 kSPS. The sensors were swept from 0 to 100℃ in 10℃ steps, while measuring the differential output voltage. A low-cost one-point calibration was performed at 30℃. As shown in Fig. 7, the temperature error of the sensors with DEM was \(-0.85/0.69\)℃, whereas the error without DEM reached \(-2.6/4.1\)℃.
During one point calibration, the \(V_{ZTC1v2}\) of each sensor is also recorded for RVC. Fig. 8 displays when the RVC scheme is not employed, the sensor exhibits a high maximum supply sensitivity of 22.1℃/V within the supply voltage range of 1.1 V to 1.35 V at 20℃ compare to measurement result at supply voltage of 1.2 V. After activation of the RVC, the maximum supply sensitivity is effectively reduced to just 3.3℃/V. The power consumption of each temperature sensor front-end is 557 nW at an operating voltage of 1.2 V. Table I. compares it with state-of-the-art temperature sensors.
5. Conclusion
This letter presents a low-power and compact full-MOS temperature sensor front-end designed for SoC application, fabricated using a 55 nm process. The proposed differential output MOSFET-based circuit with a DEM scheme achieves desirable accuracy within limited area and power consumption. The application of RVC greatly improves the power supply sensitivity performance of the sensor. The measurement results show an error of of \(-0.85/0.69\)℃ can be achieved by a low-cost single-point calibration at 30℃ and the maximum power supply sensitivity is 3.3℃/V, which is sufficient for most SoC applications. With a power consumption of 557 nW and an area occupation of 840 \(\mu m^2\), it is suitable for low-cost SoC.
Acknowledgments
This work has been funded by the e Key Special Topic of the Ministry of Science and Technology’s Major Research and Development Plan No. 2021YFB2206200.
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URL
Authors
Hao Li
Institute of VLSI Design, Zhejiang University
Zhao Yang
Institute of VLSI Design, Zhejiang University
Dezhu Kong
Zhuhai Pantum Electronics Corporation Ltd.
Aiguo Yin
Zhuhai Pantum Electronics Corporation Ltd.
Jibing Peng
Zhuhai Pantum Electronics Corporation Ltd.
Peiyong Zhang
Institute of VLSI Design, Zhejiang University