#### 1. Introduction

The advent of the DC microgrid concept has attracted attention [1], [2]. It is effective for a small area of community to produce renewable energy by themselves and buy energy via commercial power grid when needed. The 400 V has been intensively examined as the DC voltage of the DC microgrid, because it is suitable to both telco and community [3]-[6]. Energy sources of the DC microgrid are a solar photovoltaic (PV) device, a fuel cell, a battery, and so on [7]-[9]. Among these, a solar photovoltaic device is widely used everywhere in the world. However, as the output voltage of a PV module is only 20 V~40 V, the voltage boosting is necessary. In order to boost the voltage from 20 V to 400 V and to obtain enough current, PV modules are commonly connected in series and parallel, then it is connected to a DC microgrid or to a commercial grid after converting DC to AC. Using this set-up, however, the output power deteriorates due to the loss in modules and occurrence of the partially shaded area, which limits the output current of a series connected PV modules [10]-[12].

To overcome these drawbacks, the direct boosting method of a PV module voltage from 20 V to 400 V has been examined. The major candidate was the one using Z-network configuration [13]-[19]. However, the duty ratio is limited to under 50%, and the back electromotive force (EMF) of the Z-network becomes substantially small. Therefore, they needed to incorporate with a switched capacitor technique to increase the voltage [15], [17], [18], resulting in the increase of the component count.

In order to increase the duty ratio, the interleaved boost converter scheme with a switched capacitor technique has been examined [20]-[23]. As a result, the back EMF increased, and a 400 V was generated from the 20 V input using 80% duty ratio. At the same time, the component count for the switched capacitor part becomes minimum. However, the number of inductors used in the circuit was small and power conversion efficiency degraded when the output power increased.

The output power in a boost converter is transferred from the source only when the path between an inductor and the load is made. This time interval becomes small in a boost converter with a large duty ratio. Therefore, a number of inductors should be used to enhance energy transfer. The use of many inductors, however, requires multiphase control scheme [24]-[26].

On the other hand, there already exists a high-current and low-voltage buck DC-DC converter in the application of the data center use [27]-[30]. Its multiphase control and the series-capacitor connected scheme has turned out useful as a reference to realize a high gain and high current boost DC-DC converter. Taking these features into account, we have been able to construct a boost converter with high current capability and high voltage gain characteristics. The details are described below.

#### 2. Proposed boost DC-DC converter circuit

Fig. 1 shows the proposed boost DC-DC converter circuit with features of a large voltage gain and a high output power. It consists of four inductors, four switches, four capacitors including the output capacitor, four diodes, the input voltage \(V_{in}\), and the output current source \(I_{out}\). A switch consists of a MOS transistor with a protection diode. Each switch turns on when the gate voltage \(V_{gx}\) becomes high and turns off when \(V_{gx}\) is low, where x is 1-4. An Inductor and a capacitor have parasitic components such as a series resistance \(R_L\) and an effective series resistance (ESR) \(R_c\), respectively. These parasitic components have been considered in circuit simulations; however, they are not shown in the circuit in Fig. 1.

#### 3. Operation principle

The operation of the boost converter circuit shown in Fig. 1 is now described. Fig. 2 explains operation of the circuit in four different phases. The gate voltage \(V_{g1}\)-\(V_{g4}\) in Fig. 1 goes high alternatively from \(V_{g1}\) to \(V_{g4}\) in order. The high state interval of the gate voltage does not exceed one-fourth of the one control period Ts, and the circuit changes its connection such as the circuit shown from (a) to (d) in Fig. 2. Fig. 3 shows waveforms of voltages at points CLK1-CLK4 and A1-A3 for the explanation purpose.

##### 3.1 SW1=OFF, SW2, 3, and 4=ON

First, consider the case when \(V_{g1}\) turns low from the high state while \(V_{g2}\)-\(V_{g4}\) are high. In this case, the switch SW1 becomes off and all of others SW2-SW4 turn on like that as shown in Fig. 2(a). Diodes DD3-DD5 are reverse biased. Then, the terminal CLK1 is boosted to the voltage \(V_{in}/D_1\) because an inductor \(L_1\) releases its energy. At the same time, this energy charges a capacitor C2 through a diode DD2 and both voltages at the terminal A1 and across C2 become \(V_{in}/D_1\) if the forward bias voltage of DD2 is ignored. Note that \(D_1\) is the time interval when a switch remains off. This notation is different from the conventional duty ratio notation \(D\). Their relationship is \(D_1=1-D\).

##### 3.2 SW2=OFF, SW1, 3, and 4=ON

In this time interval, \(V_{g2}\) turns low while \(V_{g1}\), \(V_{g3}\), and \(V_{g4}\) remain high. Therefore, switches 1, 3, and 4 turn on, which enable to charge inductors L1, L3, and L4, while L2 is releasing its energy. Diodes DD2, DD4, and DD5 becomes reverse biased as shown in Fig. 2(b). In this case, the terminal CLK2 is boosted to \(V_{in}/D_2\), which is shown in Fig. 3. Then, the voltage at a terminal A1 becomes

\[\begin{equation*} V_{U1}=\frac{V_{in}}{D_1}+\frac{V_{in}}{D_2} \tag{1} \end{equation*}\] |

because the capacitor C2 has already charged to \(V_{in}/D_1\) in step 3.1. Again, the forward bias voltage of DD3 is ignored. Then, the voltage at terminal A1 charges capacitor C3 up to \(V_{U1}\) through a diode DD3 during this time interval, and both of voltages at a terminal A2 and across C3 become \(V_{U1}\).

##### 3.3 SW3=OFF, SW1, 2, and 4=ON

In this time interval, \(V_{g3}\) turns low while \(V_{g1}\), \(V_{g2}\), and \(V_{g4}\) remain high. Therefore, switches 1, 2, and 4 turn on which enable to charge inductors L1, L2, and L4, while L3 is releasing its energy. Diodes DD2, DD3, and DD5 becomes reverse biased as shown in Fig. 2(c). The terminal CLK3 is boosted to \(V_{in}/D_3\), which is shown in Fig. 3, and the voltage at a terminal A2 becomes

\[\begin{equation*} V_{U2}=V_{U1}+\frac{V_{in}}{D_3}=\frac{V_{in}}{D_1}+\frac{V_{in}}{D_2}+\frac{V_{in}}{D_3} \tag{2} \end{equation*}\] |

because the voltage across capacitor C3 became \(V_{U1}\) in step 3.2. The forward bias voltage of DD4 is ignored again. Then, the voltage at terminal A2 charges capacitor C4 up to \(V_{U2}\) through a diode DD4 during this time interval, and both of voltages at a terminal A3 and across C4 become \(V_{U2}\).

##### 3.4 SW4=OFF, SW1, 2, and 3=ON

Now, \(V_{g4}\) turns low while \(V_{g1}\), \(V_{g2}\), and \(V_{g3}\) remain high. Therefore, switches 1, 2, and 3 turn on which enable to charge inductors L1, L2, and L3, while L4 is releasing its energy. Diodes DD2, DD3, and DD4 becomes reverse biased as shown in Fig. 2(d). The terminal CLK4 is boosted to \(V_{in}/D_4\), and the voltage at a terminal A3 becomes

\[\begin{equation*} V_{out}=V_{U2}+\frac{V_{in}}{D_4}=\frac{V_{in}}{D_1}+\frac{V_{in}}{D_2} +\frac{V_{in}}{D_3}+\frac{V_{in}}{D_4} \tag{3} \end{equation*}\] |

as shown in Fig. 3. Again, the forward bias voltage of DD5 is ignored. As the voltage at a terminal A3 charges \(C_{out}\) through DD5, the output voltage \(V_{out}\) becomes the same voltage as that of Equation (3). When \(D'=D_1=D_2=D_3=D_4\) is selected,

\[\begin{equation*} V_{out}=\frac{4V_{in}}{D'} \tag{4} \end{equation*}\] |

In case we consider the voltage drop of diodes, one diode voltage drop is experienced each time a capacitor is charged. Therefore, Equation (4) should become

\[\begin{equation*} V_{out}=\frac{4V_{in}}{D'}-4V_{\textit{diode}} \tag{5} \end{equation*}\] |

where \(V_{\textit{diode}}\) is the forward bias voltage of a diode.

#### 4. Current distribution

##### 4.1 \(i_{L4}\) calculation

Now, the current flowing in each inductor is calculated. The current \(i_{L4}\) of the inductor \(L_4\) flows through the capacitor \(C_4\) and becomes the current \(I_{out}\) and charging current of the capacitor \(C_{out}\) during the time interval of \(D_4\) as shown in Figures 1 & 3. Therefore, the increase of the voltage across the capacitor \(C_{out}\), that is, \(V_{out}\) during this \(D_4\) period becomes

\[\begin{equation*} \Delta v_{\textit{upCout}}=\frac{i_{L4}-I_{out}}{C_{out}}D_4T_s \tag{6} \end{equation*}\] |

where \(T_s\) is one cycle time. During the rest of the time interval \(\left(1-D_4\right)T_s\) of one cycle time, the voltage across \(C_{out}\) decreases because diode \(DD_5\) is reverse biased and the current source \(I_{out}\) discharges \(C_{out}\). Therefore,

\[\begin{equation*} \Delta v_{\textit{downCout}}=\frac{I_{out}}{C_{out}}\left(1-D_4\right)T_s \tag{7} \end{equation*}\] |

is hold. The voltage change in both Equations (6) and (7) should be the same, and we obtain

\[\begin{equation*} i_{L4}=i_{C4}=\frac{I_{out}}{D_{4}} \tag{8} \end{equation*}\] |

##### 4.2 \(i_{L3}\) calculation

In the interval of \(D_3T_s\), the charge up of capacitor \(C_4\) is performed by the current flowing through \(L_3\) and \(C_3\), that is, \(i_{L3}\) (\(i_{C3}\)). Therefore,

\[\begin{equation*} \Delta v_{upC4}=\frac{i_{C3}}{C_4}D_3T_s \tag{9} \end{equation*}\] |

is obtained. During the time interval of \(D_4T_s\), the voltage across \(C_4\) decreases the same amount. It is

\[\begin{equation*} \Delta v_{\textit{down}C4}=\frac{i_{C4}}{C_4}D_4T_s, \tag{10} \end{equation*}\] |

then \(\Delta v_{upC4}=\Delta v_{\textit{down}C4}\), and

\[\begin{equation*} i_{L3}=i_{C3}=\frac{D_4i_{C4}}{D_3}=\frac{I_{out}}{D_3} \tag{11} \end{equation*}\] |

##### 4.3 \(i_{L2}\) calculation

Applying the same logic as above, we obtain

\[\begin{align} & \Delta v_{upC3}=\frac{i_{C2}}{C_3}D_2T_s \tag{12} \\ & \Delta v_{\textit{down}C3}=\frac{i_{C3}}{C_3}D_3T_s, \tag{13} \end{align}\] |

then,

\[\begin{equation*} i_{L2}=i_{C2}=\frac{D_3i_{C3}}{D_2}=\frac{I_{out}}{D_2} \tag{14} \end{equation*}\] |

##### 4.4 \(i_{L1}\) calculation

Similarly,

\[\begin{align} &\Delta v_{upC2}=\frac{i_{L1}}{C_2}D_1T_s \tag{15} \\ &\Delta v_{\textit{down}C2}=\frac{i_{C2}}{C_2}D_2T_s \tag{16} \end{align}\] |

and

\[\begin{equation*} i_{L1}=\frac{D_2i_{C2}}{D_1}=\frac{I_{out}}{D_1} \tag{17} \end{equation*}\] |

The total current which flows out from the source \(V_{in}\) becomes

\[\begin{equation*} i_{Vin}=\frac{I_{out}}{D_1}+\frac{I_{out}}{D_2}+\frac{I_{out}}{D_3}+\frac{I_{out}}{D_4} \tag{18} \end{equation*}\] |

in average. When \(D'=D_1=D_2=D_3=D_4\) holds, it is

\[\begin{equation*} i_{Vin}=\frac{4I_{out}}{D'} \tag{19} \end{equation*}\] |

#### 5. Power dissipation

In this section, limitations posed to elements and the power dissipation of the circuit are examined.

##### 5.1 Maximum reverse bias voltage of devices

Here, all the duty is assumed to be equal, that is, \(D'=D_1=D_2=D_3=D_4\). The maximum voltage for the inductor \(L_1\) becomes \(V_{in}(1-D')/D'\). The same voltage is observed for each inductor from \(L_2\) to \(L_4\). Then, the maximum voltage for transistors and diodes of switches SW1-SW4 becomes \(V_{in}/D'\). The maximum reverse bias voltage of capacitors \(C_2\), \(C_3\), \(C_4\), and \(C_{out}\) are \(V_{in}/D'\), \(2V_{in}/D'\), \(3V_{in}/D'\), and \(4V_{in}/D'\), respectively. Moreover, the reverse bias voltage of diodes \(DD_2\), \(DD_3\), \(DD_4\), and \(DD_5\) are \(2V_{in}/D'\), \(2V_{in}/D'\), \(2V_{in}/D'\), and \(V_{in}/D'\), respectively. The voltage stresses to devices are low.

##### 5.2 Power dissipation

Let a series resistance of an inductor and an on resistance of a transistor be \(r_L\) and \(r_{ON}\), respectively. The equivalent series resistance of a capacitor is assumed to be zero. Then, the power dissipation due to \(r_L\) and \(r_{ON}\) becomes

\[\begin{equation*} 4r_L\left(\frac{I_{out}}{D'}\right)^2+4r_{ON}\left(\frac{I_{out}}{D'}\right)^2(1-D') \tag{20} \end{equation*}\] |

As power dissipation of a forward bias diode is \(V_{\textit{diode}}I_{\textit{diode}}\), the total power dissipation of the circuit shown in Fig. 1 becomes

\[\begin{equation*} 4r_L\left(\frac{I_{out}}{D'}\right)^2+4r_{ON}\left(\frac{I_{out}}{D'}\right)^2 (1-D')+4\left(V_{\textit{diode}}\frac{I_{out}}{D'}\right)D' \tag{21} \end{equation*}\] |

##### 5.3 Output voltage ripple

Charging up of the output capacitor \(C_{out}\) is done during \(D_4T_s\) interval. The voltage difference between charging and discharging process is the same in the steady state operation. During the rest of the \(\left(1-D_4\right)T_s\) interval, \(C_{out}\) is discharged by the current source \(I_{out}\). The amount of the voltage decrease is

\[\begin{equation*} \Delta V_{\textit{outripple}}=\frac{I_{out}}{C_{out}}\left(1-D_4\right)T_s \tag{22} \end{equation*}\] |

This ripple value does not differ from that of the conventional one-stage boost converter.

#### 6. Simulation results

The circuit simulation has been done to verify effectiveness of the proposed high gain and high output power boost DC-DC converter shown in Fig. 1. Table I lists devices and parameters used in simulations. L and C values are chosen to 1 mH and 10 \(\mu\)F, respectively. Considering parasitic components, an 100 m\(\Omega\) series resistance for each inductor from L1 to L4, and a 10 m\(\Omega\) effective series resistance (ESR) for each capacitor from C2 to C4 and Cout were used. Clock frequency was 50 kHz. Device parameters of transistors and diodes are those of commercial products, and simulation results are considered close to the performance of actual circuits.

Fig. 4 shows the relationship between the voltage gain and turn off duration \(D'\), where \(D'\) is the time interval when transistor switches SW1~SW4 in Fig. 1 remains off. The curve “ideal” is the plot of Equation (4) when \(D'=D_1=D_2=D_3=D_4\). The sum (\(D_{1}+D_{2}+D_{3}+D_{4}\)) should not exceed 1. As shown in Fig. 4, the ideal voltage gain with \(D'=0.2\) is 20 while the simulated voltage gain was 19.9. There is no big difference between the ideal and simulated ones. However, the circuit in simulation accompanied with series resistances of inductors, ESRs of capacitors. Moreover, commercially available device parameters of transistors and diodes were used. Yet, deterioration of the voltage gain is very small.

Fig. 5 shows the dependency of the output voltage on the output current. Vin was 20 V. Circles show those of simulated characteristics of the 4-coil circuit in Fig. 1. Parasitic components are all included. As the output current increases, the loss in the circuit increases and the output voltage decreases. Even when the output voltage decreases to 350 V, it is still able to draw about 2.5 A of the output current. This means that the output power of 875 W is available. On the contrary, crosses in Fig. 5 are simulation results of the 3-stage version of the 2-coil circuit from Fig. 2 in reference [20]. The relationship between the output voltage and output current was plotted for comparison.

In this simulation, exactly the same parameters as those of the 4-coil circuit shown in Fig. 1 were used. As can be seen in Fig. 5, the circuit in [20] used only two coils and currents flowing through inductors and transistors are double of those of the 4-coil circuit, its output voltage fell down two times faster than that of the 4-coil circuit.

Fig. 6 shows the relationship between the output current vs. power. Simulation results of the input power (Pin) and output power (Pout), and the power dissipation in series resistances of four inductors (PRL), four switches (PSW) and four diodes (PDD) of the 4-coile circuit shown in Fig. 1 are plotted. For comparison, the output power of the 2-coil circuit in [20] is plotted. As transistors used in simulations have large current capability, the on resistance of the transistor does not change much depending on its drain current and is considered to be constant in the range up to 10 A of the output current. Therefore, both curves of PRL and PSW in Fig. 6 become the quadratic function. These curves well agree with the results of Equations (20) and (21). As the power dissipation of diodes PDD are small because they operate only during their turn on duration D\('\), it does not affect much to the circuit behavior. From the figure, it is clear that major causes of power loss are series resistances of inductors and on resistance of transistor switches.

Table II compares the power efficiency between the 4-coil circuit shown in Fig. 1 and the 2-coil circuit in [20] when the output current changes. As seen in Fig. 6, on resistances of transistors are considered constant even when their drain currents change. It was around 60 m\(\Omega\). Moreover, major sources of power consumption of the circuit are series resistances of coils and on resistances of transistors, the degradation of power efficiency in both DC-DC converters in Table II seems proportional to the output current change especially in the region of more than 1 A. Table II again tells that the 4-coil circuit has a larger output current capability than the 2-coil circuit.

Overall, simulation results verified that the boost converter shown in Fig. 1 realized a large voltage gain and power driving capability at the same time.

Table III further compares the performance in various works that deal with solar panels. S-SCZS is based on the Z-source configuration. However, transistor and the load become floating and it is not suitable to use DC grid system. On the other hand, Dickson type is suitable for DC grid system, however, the output current capability is small and the power efficiency degrade rapidly as the output current increases as shown in Table II. On the contrary, this work improved the output current capability to twice as much of Dickson type. If the same output current capability as this work is needed, Dickson type has to use two converters in parallel, and the component count surpasses that of this work.

#### 7. Conclusion

A DC-DC boost converter circuit which realizes high voltage gain and high driving capability has been proposed and analyzed. The use of parallel series-capacitor configuration and multiphase control of coil voltages enabled high output current capability with keeping high voltage gain, high power efficiency, low stress on devices and low component count. As these characteristics are verified by circuit simulations with commercially available device parameters, the proposed boost converter circuit turned out suitable to the use of the interface between PV cells and DC microgrid.

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#### Authors

Toru Sai

Dept. Engineering, Tokyo Polytechnic University

Yasuhiro Sugimoto

Chuo University