#### 1. Introduction

Digital communication systems and instrumentation applications promote the development of high-performance analog-to-digital converters (ADCs) [1]-[3]. Among many ADC architectures, Pipelined ADC is very suitable for high-speed and high-precision operations. However, without calibration, due to the limitation of capacitor mismatches, it is arduous for ADC with a sampling rate exceeding 100 MS/s to exceed an accuracy of 12 bit. Meanwhile, as the CMOS technology keeps scaling down, high-gain amplifiers become increasingly toilsome to design. The two seriously deteriorate the linearity of pipelined ADC [1], [4]. In order to boost the performance of high-speed pipelined ADCs, calibration techniques are needed.

A typical method is dither-based calibration technique, which features low power consumption and area penalty. By injecting small dither signals, this method can fulfil interstage gain error calibration [3], [5]-[8]. J. Li *et al*. [8]-[10] have implemented a comparator dither injection technique, which achieves the goal of improving ADCs linearity by dynamically changing the threshold voltage of comparator in Pipelined ADCs. Another injection method is capacitive dithering method, which was proposed in [11], [12]. However, both the comparator threshold and capacitive dither injection induce an obvious increment of the residual amplifier’s output, which occupies the redundancy range, leading to higher-order nonlinearity and even saturation of the following stages [12]-[15], [26].

The signal-dependent dithering proposed in [16], [17] eliminates the residual increment. Notwithstanding, the complexity of the analog circuits is evidently increased by injecting the dither through the addition of two comparators and the division of the unit capacitor into two within each 1.5-bit stage. Furthermore, the use of twice the number of comparators to counter the increment of residual amplitude not only eventuates in significant power consumption but also dilutes the sampling linearity [18]-[20].

In this brief, a new digital background calibration technique based on LMS, called complementary dithering here, is developed to achieve calibration of interstage gain error while eradicating the increment of residual amplitude. Concurrently, the technique of constructing calibration windows exploiting the comparator resolving time nature has been proposed, which averts the use of duplicate comparators and its digital logic is simple.

This brief is organized as follows. Section 2 details traditional dither injection structures. Section 3 depicts complementary dithering technique and calibration windows detector. Behavioral simulation results are presented in Section 4, followed by conclusions in Section 5.

#### 2. Traditional dither structure

Injection pseudo-random noise (PN) signal into ADCs, this approach leverages the characteristic of PN signals being independent of input signals to extract parameter information regarding non-ideal factors within the ADC [22]-[24], which involves a diverse array of injection positions and error parameter extraction methods. Among the mature techniques currently in use, two prominent approaches are the injection of sub-DAC dither [6] and sub-ADC dither [8], [9], [25]. These two methods effectively reduce the complexity of analog circuit design.

##### 2.1 Sub-DAC dither injection

The calibration schematic diagram for injection PN signals into the sub-DAC is illustrated in Fig. 1 [6], [17], [25]. The transfer function of the MDAC in this case is as follows:

\[\begin{equation*} V_{\textit{res}}=\frac{A\beta}{C_f(1+A\beta)}\cdot V_{\textit{res}}' \tag{1} \end{equation*}\] |

\[\begin{equation*} V_{\textit{res}}'=\left(\sum_{i=1}^M C_i V_{in}-\sum_{i=1}^M C_i D_i - PN\cdot C_{\textit{injection}}\cdot V_{\textit{ref}}\right) \tag{2} \end{equation*}\] |

Where \(C_i\), \(C_{\textit{injection}}\), \(C_f\), \(A\), and \(\beta\) represent the sampling capacitor, dither injection capacitor, feedback capacitor, finite open-loop gain, and feedback coefficient, respectively, for that particular stage. In addition, \(D_i\) represents the comparison result between the input signal \(V_{\textit{in}}\) and the threshold voltage \(V_{\textit{th}}\) of the \(i^{\textit{th}}\) comparator in the sub-ADC. When \(V_{\textit{in}} > V_{\textit{th}}\), \(D_i\) is 1, otherwise, \(D_i\) is 0. M represents the number of sampling capacitors in the sub-DAC, equivalent to 4 for 1.5-bit/stage of the ADC.

By leveraging the autocorrelation and cross-correlation properties of the PN signal, practical interstage gain errors can be obtained when the PN sequence is sufficiently long:

\[\begin{equation*} \frac{1}{N}\sum_{j=1}^N\left[V_{\textit{res}}*(-PN)\right]= \left(1-\Delta G\right)\frac{C_{\textit{inject}}\cdot V_{\textit{ref}}}{C_f} \tag{3} \end{equation*}\] |

Where \(G\) and \(\Delta G\) respectively represent the ideal interstage gain of this stage ADC and the interstage gain error caused by the limited open-loop gain of the operational amplifier, and are respectively equal to \(\frac{\sum_{i=1}^M C_i}{C_f}\), \(\frac{1}{A\beta}\). This allows for the extraction of interstage gain error information for the operational amplifiers. However, when injecting PN modulation signals into the sub-DACs and overlaying them on the signal path, it is necessary to ensure that the residue signal \(V_{\textit{res}}\) at the output of this stage does not exceed the input dynamic range of the next pipeline stage. This requirement reduces the amplitude of the input signal \(V_{\textit{in}}\), ultimately degrading the signal-to-noise ratio (SNR) of the ADC.

##### 2.2 Sub-ADC dither injection

The calibration schematic for injecting PN signals into the sub-ADC is depicted in Fig. 2 [17], [25]. At this point, digital output of the sub-ADC \(D_{\textit{sub}}\) and the backend ADC \(D_{b_{\textit{end}}}\) are represented by equations (4) and (5) respectively:

\[\begin{equation*} D_{\textit{sub}}=\frac{V_{\textit{in}}}{V_{\textit{ref}}}+PN\cdot \frac{V_{\textit{cal}}}{V_{\textit{ref}}}+Q_s \tag{4} \end{equation*}\] |

\[\begin{equation*} D_{b_{\textit{end}}}=-\frac{G\left(PN\cdot V_{\textit{cal}}+Q_s\cdot V_{\textit{ref}}\right)}{V_{\textit{ref}}}+Q_b \tag{5} \end{equation*}\] |

Where \(Q_s\) stands for the quantization error of the sub-ADC, and \(Q_b\) is the quantization error of the backend ADC. Correlating the ADC digital output with the PN signal, as follows:

\[\begin{equation*} PN*D_{\textit{out}}=PN\left(D_{b_{\textit{end}}}+D_{\textit{sub}}G_{\textit{es}}\right) =\frac{PN^2\left(G_{\textit{es}}-G\right)V_{\textit{cal}}}{V_{\textit{ref}}} \tag{6} \end{equation*}\] |

It is evident that error parameters can also be extracted, and after calibration, the estimated value \(G_{es}\) approaches the true value infinitely closely.

It can be observed that the second dither injection scheme is similar to the first one, except that the injection position of the PN signal is changed. However, since the comparator threshold dither only affects the input signals within its dither coverage range, the dither effect is relatively small, and the scattering effect on the spectrum is poor. At the same time, both schemes will cause the output range of the operational amplifier to increase, which takes up the redundancy range.

#### 3. Proposed complementary dither technique and calibration windows detector

##### 3.1 Complementary dither technique

In order to address the problems existing in the above scheme, as presented in Fig. 3, the complementary dither technique is introduced using a modified 1.5-bit stage as an example. To avoid residual output overflow due to PN signal injected into the DAC, the 1.5-bit stage here adds two comparators and two capacitors.

Figure 4(a) compares the two 1.5-bit stage residual transfer functions (RTF) of a conventional stage with a PN signal of \(\pm V_{\textit{DAC}}\) injected into the DAC. Evidently, due to the injection of PN signal, the residual transfer function will move up or down, causing the RTF to shift from \(\pm 1/2V_{\textit{ref}}\) expanded to \(\pm(1/2V_{\textit{ref}}+V_{\textit{DAC}})\). However, supposing that the PN signal with a size of \(\pm V_{\textit{ADC}}\) is injected into the sub-ADC to change the comparator threshold, the residual transfer functions is shown in Fig. 4(b). Apparently, the transition point of the RTF will move left or right, which will also induce the RTF from \(1/2V_{\textit{ref}}\) dilated to \(\pm (1/2V_{\textit{ref}}+| V_{\textit{ADC}}| \cdot \textit{Ge}\)), where \(\textit{Ge}\) is the interstage gain coefficient of this stage.

Provided that the direction of the both dither injections are opposite and amplitude satisfies \(V_{\textit{DAC}}=V_{\textit{ADC}}\cdot \textit{Ge}\), the residual increment disappears, as presented in Fig. 5. The both dither injections will have a complementary effect, limiting the output of the residual amplifier to within \(\pm(1/2V_{\textit{ref}})\) range. The result is that complementary dither injection does not occupy any redundancy range of the pipelined ADC.

From Fig. 5, it can be seen that if the input signal undergoes the corresponding selection, so that the input signal is limited within the purple arrow range, this range is defined as the calibration window. Furthermore, the input signal within the calibration window is only affected by the DAC dither injection, and is not affected by the sub-ADC dither injection. If the pseudo-random noise signal injection by the sub-ADC has an amplitude of \(V_d\), the calibration window statistics are as shown in Table I:

If only the corresponding correlation operations are performed on the signals within the calibration window, it is equivalent to only injecting dither into the DAC. Due to the dither passing through the same path as the DAC signal, the identical non ideal situation will be encountered, and the interstage gain error can be detected to achieve the extraction of interstage gain error. The scheme restricts residual output to \(\pm 1/2V_{\textit{ref}}\), which greatly mitigates the design requirement of the residual amplifier. More than that, the injected dither exhibits higher amplitude, making interstage gain error coefficient easier to extract, thereby significantly enhancing the convergence speed.

While correlation operations can estimate interstage gain errors in this process, they may also introduce certain issues, such as trade-off between convergence speed and precision. Hence, the utilization of the least mean square (LMS) algorithm for the extraction of interstage gain errors is depicted in the schematic diagram as shown in Fig. 6 [27]. The numerical value of PN signal in digital domain is called \(\mathrm{D}_{\text{compensation}}\). The calibration process is as follows:

\[G[n+1]=G[n]\pm\mu\cdot PN[n]\cdot (\textit{Dob}1-PN[n]\cdot G[n])\] |

where \(G[n+1]\) is the \((n+1)^{\textit{th}}\) estimated value of the interstage gain coefficient, \(\textit{Dob}1\) is the digital output of the stage being calibrated, \(\mu\) is the convergence step size factor controlling the calibration algorithm’s convergence speed and accuracy.

The digital output signal \(\textit{Dob}1\) is obtained from the back-end pipeline with all the needed correction applied to make it as accurate a representation of the residue as possible. The dither is multiplied by the estimate of the interstage gain coefficient and is subtracted from the output signal. The result is multiplied by the ideal dither and by \(\mu\), then passes through an accumulator to give an estimate for the interstage gain coefficient Ge. The dither estimate is subtracted from the residue, which is corrected by the estimate of the interstage gain error to give the calibrated digital output Dob1_cal. The LMS iteration forms a feedback loop whose iteration speed is governed by the step size \(\mu\). A higher \(\mu\) leads to a swifter convergence but lower calibration precision and vice versa.

##### 3.2 Calibration windows detector

B. Murmann *et al*. [18], [19], [21] employed two-fold comparators to screening the input signal range affected solely by the injection of DAC dither. However, this scheme not only results in increased power consumption but also diminishes the sampling linearity. We introduce a calibration windows detector (CWD), which leverages the meta-stability nature of comparator to construct calibration windows [28]-[30]. When \(V_{\textit{in}}\) approaches the \(V_{\textit{th}}\), the comparator’s differential input is minimal, necessitating more time for the comparator to resolve a valid logic level. Hence, the comparison time inherently encodes information about the signal range, as illustrated in Fig. 7. Taking the example of the \(i^{\textit{th}}\) comparator with the threshold voltage \(V_{\textit{thi}}\) in the sub-ADC, Fig. 7 provides a comprehensive schematic and timing diagram to elucidate the principles of this approach. Figure 8 demonstrate the structure of sub-ADC with calibration windows detector.

The calibration windows detector comprises an XOR gate, a Flip-Flop and a manually adjustable delay buffer. The clock is simultaneously connected to both the comparator and the buffer, with the buffer introducing a delay of \(T_b\), which can the manually controlled. The comparator only operates when the clock signal arrives at the rising edge, but the comparison result is transferred to the input of the Flip-Flop only after a delay of one resolving time \(T_r\). By comparing the reference time \(T_b\) of the delay buffer with the resolving time \(T_r\) of the comparator, the range of the input signal can be determined. The relationship between the resolving time \(T_r\) of the comparator and the input signal \(V_{\textit{in}}\) is given by:

\[T_r=t_0+\tau\cdot\ln \left(V_{\textit{FS}}/\left| V_{\textit{in}}-V_{\textit{th},i}\right|\right)\] |

where \(t_0\) is the delay time of all the logic circuits, \(\tau\) is the time constant of the latch and \(V_{\textit{FS}}\) is the full-scale output [31]. The corresponding comparator resolving time when \(\left|V_{\textit{in}}-V_{\textit{th},i}\right| =V_d\) is denoted as \(T_d\). When \(T_d< T_r\), it indicates that \(\left|V_{\textit{in}}-V_{\textit{th},j}\right| < V_d\). Accordingly, when the clock edge arrives at the trigger, the output of the \(i^{\textit{th}}\) comparator remains in the reset state. Consequently, the output of the trigger should be in a low logic level. Conversely, when \(T_d> T_r\), signifying \(\left|V_{\textit{in}}-V_{\textit{th},j}\right| > V_d\), the trigger’s output should be in a high logic level.

Clearly, it is possible to determine the input signal’s range based on the trigger’s output, thus deducing the calibration windows. This not only facilitates the extraction of interstage gain errors within the entire input range, significantly enhancing calibration convergence speed but also eliminates the need for using double the number of comparators.

#### 4. Simulation results

To validate the effectiveness of the proposed calibration scheme, several behavioral simulations are provided for a 12-bit 1.25 GS/s pipelined ADC that is comprised of 8 1.5-bit stages and 4-bit flash ADC as the last stage. Due to the inherent characteristics of the pipelined architecture, the precision requirements decrease as stages progress. Therefore, calibration was applied to the interstage gain error in the first four stages only. To simplify the simulation, the interstage gain errors and the capacitor mismatch for the first four stages are assumed to be 2% and 0.1%, and the subsequent stages were considered ideal. In addition, a foreground calibration is employed for the initial four stage capacitance mismatch.

Figure 9 depicts the simulated spectrum of the ADC output before calibration. The SNDR and SFDR are approximately 44.27 dB and 49.43 dB, respectively. After utilizing the complementary dither technique and the calibration windows detector technique, the spectrum is shown in Fig. 10. The SNDR and SFDR have been improved to approximately 70.8 dB and 115.3 dB, achieving 26.53 dB and 65.9 dB enhancements, respectively.

The depicted Fig. 11(a) shows that the differential nonlinearity (DNL) and the integral non-linearity (INL) of the defined converter before calibration are \(+0.94/-1\) LSB, and \(+21/-21.5\) LSB, respectively. Applying the proposed calibration, the ADC’s DNL and INL, are tuned to about \(+0.2/-0.19\) LSB and \(+0.14/-0.15\) as shown in Fig. 11(b).

Figure 12 presents the iterative convergence plots of the interstage gains coefficient, \(\textit{Ge}_1\), \(\textit{Ge}_2\), \(\textit{Ge}_3\), and \(\textit{Ge}_4\), for the converter after calibration. Clearly, \(\textit{Ge}_1\), \(\textit{Ge}_2\), \(\textit{Ge}_3\), and \(\textit{Ge}_4\) have all converged to their theoretical values 1.96.

Table II furnishes the comparison results to the other technique currently available. In summary, the proposed calibration technique has almost no residue output increment, which will greatly alleviate the design requirements of residual amplifier. Moreover, this scheme yields a more substantial enhancement in the dynamic performance of the ADC, particularly in terms of SFDR and SNDR. More importantly, it eschews any additional analog circuits making this formula to be more benefited from the CMOS process scaling.

#### 5. Conclusion

In this paper, we propose a background calibration technique for interstage gain errors based on complementary dither injection with calibration windows detector. Complementary dithering not only has a better scattering effect on spectral spurs but also cancels the residual amplitude increment of residual amplifier. what’s more, this approach significantly enhances the SFDR and SNDR of the ADC while also alleviating the design requirements for the residual amplifier. In addition, the proposed calibration windows detector technique can avoid the use of twice the number of comparators. Compared with existing calibration techniques, it does not change the analog circuit and only has a small digital circuit overhead.

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#### Authors

Huaiyu Zhai

Institute of Microelectronics of the Chinese Academy of Sciences

University of Chinese Academy of Science

Hanbo Jia

Institute of Microelectronics of the Chinese Academy of Sciences

Xuan Guo

Institute of Microelectronics of the Chinese Academy of Sciences

Zilin Jiang

Institute of Microelectronics of the Chinese Academy of Sciences

University of Chinese Academy of Science

Yuzhen Zhang

Institute of Microelectronics of the Chinese Academy of Sciences

University of Chinese Academy of Science

Dandan Wang

Institute of Microelectronics of the Chinese Academy of Sciences

University of Chinese Academy of Science

Jin Wu

Institute of Microelectronics of the Chinese Academy of Sciences

University of Chinese Academy of Science