#### 1. Introduction

With the growing trends of power efficient SoC solutions, SoC solutions require the full integration of low-power power management integrated circuits (PMICs) [1]-[3]. Switching power converter (SWPC) are often used as power storage interfaces due to their high efficiency, however, this generates a high level of switching noise. To provide good isolation between the SWPC noisy output and the very noise-sensitive RF and/or high-performance analog blocks, the PSR of LDO is becoming a very demanding specification [4], [5]. Besides PSR, transient response is one of the most important specifications for LDOs [6].

Many excellent designs of LDOs with high PSR and fast-transient response have reported in literature, such as a fast-transient response LDO with 67.9 dB of PSR at 10 MHz in [7]. However, many of them [7]-[12] needs \(\mu\)F\({-}\)level off-chip capacitor for stability, PSR enhancement and transient improvement, which may be not good solutions in SoC. Capacitor-less LDOs are the preferred architecture solution as they can be fully integrated, and as a result, bill of material and printed circuit board (PCB) area are reduced [13], [14]. There are some capacitor-less LDOs [15]-[20]. [15]-[18] only achieve high PSR [15], [16] or fast-transient response [17], [18]. [19], [20] have excellent PSR performance and transient response. However, they have high quiescent current (I_{Q}), which cannot properly address all the issues present in power efficient noise-sensitive applications.

In this paper, a fast-transient dual loop LDO with high PSR is proposed. The proposed LDO includes a fast loop and a slow loop. The fast loop adopts a class-AB error amplifier to increase the slew rate at the power transistor gate terminal for fast-transient response. The slow loop is adopted to modulate the tail current source of the class-AB error amplifier, which can increase the PSR of the LDO. Due to the dual loop design, high PSR can be achieved, yet the high-slew-rate fast loop is still preserved, which can ensure fast-transient response. As a result, the proposed LDO achieves both fast-transient response and favorable PSR performance.

This paper is organized as follows. Section 2 describes the circuit implementation. Section 3 presents the loop stability and PSR analysis. Section 4 summarizes the simulation results. Section 5 is the conclusion of this paper.

#### 2. Fast-transient dual loop LDO with high PSR

A typical LDO [21], whether a fully integrated one or with external capacitor, consists of an error amplifier (EA) and power transistors, as shown in Fig. 1.

When the load current changes rapidly, the M_{P} cannot immediately increase or decrease sufficient current. Therefore, it will cause the output voltage to fluctuate and the output voltage requires response time to be regulated by the negative feedback control, then the response time \(\Delta\)t can be expressed as:

\[\begin{equation*} \Delta t\approx \frac{1}{BW_{cl}}+C_{\textit{par}}SR \tag{1} \end{equation*}\] |

where BW_{cl} is the closed-loop bandwidth, C_{par} is the parasitic capacitance at the power MOSFET gate terminal and SR is the slew rate at the power MOSFET gate terminal. From Eq. (1), it can be seen that increasing the slew rate can reduce the response time and improve the transient response capability of the LDO. To increase the slew rate, a conventional method is to increase the bias current of the amplifier. However, efficiency of those LDOs at small I_{LOAD} is degraded. In addition, LDO can regulate the output voltage through the negative feedback control. Any switching disturbance from SWPCs can be effectively reduced by an effective loop gain [22]. Based on the above analysis, a dual loop LDO is proposed to achieve fast-transient and high PSR. The proposed LDO is based on the concept described in [23]-[27], which focuses on the slew-rate improvement. In order to improve the PSR performance, in this work, a high gain loop is added.

Figure 2 shows the architecture of the proposed dual loop LDO. The LDO system can be divided into two parts: the fast loop consisting of class-AB error amplifier EA_{1} and power transistor M_{p} and the slow loop consisting of full differential error amplifier EA_{2}, class-AB error amplifier EA_{1} and power transistor M_{p}.

In the fast loop, the difference between the output voltage and V_{ref} is converted into error current by class-AB error amplifier EA_{1}, and the larger pulling current of class-AB error amplifier is used to charge and discharge the parasitic capacitor to improve the slew rate, thus obtaining a better transient response performance. In the slow loop, the full-differential error amplifier EA_{2} is a folded-cascode amplifier. EA_{2} modulates the tail current source of the fast loop to achieve good regulations and high PSR. A Miller capacitor C_{C} and a null resistor R_{Z} is added for frequency compensation to increase the phase margin and the system stability [28]-[30].

Figure 3 shows the schematic of the proposed LDO. For the fast loop, the EA_{1} consists of M_{1-12}, where M_{3-8} as two common-gate differential-input transconductance (G_{m}) cells to amplify the output variation, M_{9-12} as a current-summation circuit to redirects the output current of G_{m} to the amplifier output. With respect to the slow loop, to achieve a good dc accuracy, the difference between the output V_{OUT} and reference voltage V_{REF} is sensed by EA_{2}, and connected to the gate of the M_{1-2}. A decoupling capacitor C_{EA} is added to the gate of M_{1-2} to form a dominant pole for the slow loop, which is at much lower frequency than the poles in the fast loop, and thus stabilizes the slow loop easily.

#### 3. Stability and PSR analysis

Figure 4 shows the Small-signal model of the proposed LDO.

To analyze the fast loop, the signal path is broken from V_{OUT} to the input of A_{1} and the ac signal V_{t1} is added. The loop gain, poles, and zeros are given in:

\[\begin{eqnarray*} && T_1(s)=\frac{v_{f1}}{v_{t1}}=\left(g_{mH}+g_{mL}\right)g_{mP}R_{o1} \left(R_L\parallel R_{\mathrm{IN},{\mathrm{G_m}}}\right)\nonumber\\ &&\hphantom{T_1(s)= } \frac{1+s/z}{\left(1+s/p_1\right)\left(1+s/p_2\right)} \tag{2} \end{eqnarray*}\] |

\[\begin{equation*} p_1\!=\!-\frac{1}{R_{o1}\left(C_{\textit{pass}}+ \left(1+g_{mP}R_LR_{\mathrm{IN},\mathrm{G_m}}/\left(R_{\mathrm{IN},\mathrm{G_m}}+R_L\right) \right)C_c\right)} \tag{3} \end{equation*}\] |

\[\begin{equation*} p_2=-\frac{g_{mP}C_c}{C_{\text{pass}}C_c+C_{\text{pass}}C_L+C_cC_L} \tag{4} \end{equation*}\] |

\[\begin{equation*} z=\frac{1}{C_c\left(1/g_{mP}-R_z\right)} \tag{5} \end{equation*}\] |

Equation (2) shows that Miller capacitor C_{C} pushes P_{1} to a relatively low frequency and that null resistor R_{Z} converts the RHP zero into LHP zero, such that it improves the stability. To analyze the slow loop, the signal path is broken from the output of A_{2} to the gate of current source and the ac signal V_{t2} is added. The loop gain and poles are given in:

\[\begin{equation*} T_2(s)=\frac{v_{f2}}{v_{t2}}\approx-g_{mA2}R_{O2}\frac{g_{m1,2}}{g_{m6,7}} \frac{1}{\left(1+s/p_1\right)\left(1+s/p_2\right)} \tag{6} \end{equation*}\] |

\[\begin{equation*} p_1=-\frac{1}{R_{o2}C_{O2}} \tag{7} \end{equation*}\] |

\[\begin{equation*} p_2\!=\!-\frac{\left(g_{mH}+g_{mL}\right)g_{mP}R_{o1} \left(R_{L}\parallel R_{\mathrm{IN},{\mathrm{G_m}}}\right)}{R_{o1} \left(C_{\textit{pass}}+\left(1+g_{mP}R_{L}R_{\mathrm{IN},\mathrm{G_m}}/ \left(R_{\mathrm{IN},\mathrm{G_m}}+R_L\right)\right)C_c\right)} \tag{8} \end{equation*}\] |

The worst case occurs at light loads where g_{mP} is minimized, and designing a suitable GBW for slow loop ensures the stability. Analyzing the PSR, the transfer function is

\[\begin{align} &\mbox{$ \displaystyle \mathit{PSR} =\frac{v_{\mathrm{out}}}{v_{\mathrm{in}}}=\frac{-\mathit{PSR}_{A2}A_1A_{mp}+A_{mp}+R_L\parallel R_{\mathrm{IN},\mathrm{G_m}}/r_{\mathrm{op}}+R_L\parallel R_{\mathrm{IN},\mathrm{G_m}}}{1+A_1A_{mp}+A_2A_1A_{mp}} $}\nonumber \\ &\displaystyle \hskip8.5mm \approx -\frac{\mathit{PSR}_{A2}}{A_2}+\frac{1}{A_1A_2} \tag{9} \end{align}\] |

where PSR_{A2} is the PSR of EA_{2}, A_{1} is the DC gain of EA_{1}, A_{2} is the DC gain of EA_{2}. Equation (9) shows that PSR is mainly affected by PSR_{A2} and A_{2}. So PSR is improved by adding EA_{2}.

#### 4. Simulation results

The results obtained by simulation of the proposed LDO are presented in this section. Fabrication process fluctuations were considered, and LDO was simulated using Corner Analysis. The temperature ranges from \(-40^\circ\)C to 125\(^\circ\)C was considered in all simulations.

Figure 5 shows the simulated transient response of the output voltage with load current changes from 500 \(\mu\)A to 50 mA within 50 ns. At 27\(^\circ\)C, the voltage undershoot and overshoot are 96 mV and 53.6 mV, and the LDO can recover to 1% accuracy within 70 ns and 81 ns, respectively. As can be seen, the worst case is reported at 125\(^\circ\)C, where the voltage undershoot of 109.5 mV and overshoot of 65.8 mV were reached. One can observe that LDO has fast-transient response.

The simulated bode plot of the LDO slow loop with CL=30 pF at different I_{LOAD} are shown in Fig. 6. The low frequency loop gain is over 70 dB while the phase margins are more than 60\(^\circ\).

The simulated bode plot of the LDO fast loop with CL=30pF at different I_{LOAD} are shown in Fig. 7. The GBW with I_{LOAD}=500 \(\mu\)A, and 50 mA are 67 MHz and 150 MHz while the phase margins are more than 50\(^\circ\).

For the purpose of stability, we investigate phase margin (PM) of the fast loop and slow loop. To verified stability for marginal values of the output current, we also consider load current of 500 \(\mu\)A and 50 mA. The results of PM obtained from stability analysis of the fast loop for all process corners and temperature range from \(-40^\circ\)C to 125\(^\circ\)C are shown Fig. 8. The best case and the worst case for PM of the fast loop are reported for the current value of 50 mA. The worst case for PM of the fast loop is reported at \(-40^\circ\)C in the SNSP corner, where the value of 45.02\(^\circ\) was reached. The best case for PM of the fast loop is reported at 125\(^\circ\)C in the FNSP corner, where the value of 73.51\(^\circ\) was reached.

The results of PM obtained of the slow loop for all process corners and temperature range from \(-40^\circ\)C to 125\(^\circ\)C are shown Fig. 9. The best case and the worst case for PM of the fast loop are reported for the current value of 500 \(\mu\)A. The worst case for PM of the slow loop is reported at \(-40^\circ\)C in the FNSP corner, where the value of 69.78\(^\circ\) was reached. The best case for PM of the slow loop is reported at 125\(^\circ\)C in the FNFP corner, where the value of 76.7\(^\circ\) was reached.

In order to show the improvement obtained using a high gain slow loop, we compared the PSR performance with and without the slow loop. The result of comparison is depicted in Fig. 10, where one can observe that the PSR performance will be improved by 60 dB at 1 kHz and by 20 dB at 1 MHz. From Fig. 10 we can conclude that the high gain slow loop working as expected for improving PSR performance of the LDO.

The PSR results with I_{LOAD}=500 \(\mu\)A obtained for all process corners and temperature range from \(-40^\circ\)C to 125\(^\circ\)C are shown in Fig. 11. As can be observed, the PSR at 1 kHz reaches value of over 130 dB, while at frequency of 1 MHz, the PSR of over 50 dB was achieved. In the worst case, PSR of \(-50.9\) dB at 1 MHz was achieved at 125\(^\circ\)C in the SNSP corner. In the best case, PSR of \(-57.2\) dB at 1 MHz was achieved at \(-40^\circ\)C in the FNFP corner.

Table I summarizes and compares the results of this work with previous implementations of similar specifications reporting the complete set of LDO static and dynamic parameters, and the results are all selected from a temperature of 27\(^\circ\)C, a process angle of typical NMOS & typical PMOS model. Among all works, the proposed LDO has relatively low power consumption while achieving fast-transient response and good PSR performance.

#### 5. Conclusion

A 0.18 \(\mu\)m CMOS dual loop capacitor-less LDO for SoC power supply is proposed. The proposed LDO utilizes a high slew rate fast loop to achieve the fast-transient response. High PSR is achieved by using a high gain slow loop. Obtained results show that the proposed LDO reaches relatively low power consumption. With the dual loop design, the proposed LDO achieves that undershoot and overshoot voltages are 96 mV and 53.6 mV and the proposed LDO can recover to 1% accuracy within 70 ns and 81 ns respectively while over 50 dB PSR at 1 MHz.

#### Acknowledgments

This study was funded by the Special Fund for Research on National Major Research Instruments of the National Natural Science Foundation of China (NSFC) (Grant number: 82327810), and the Key Research and Development Projects of Shaanxi Province (Grant number: 2020GY-080).

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#### Authors

Hang Fang

School of Microelectronics, Xidian University

Gang Jin

School of Microelectronics, Xidian University

Weifeng Liu

School of Microelectronics, Xidian University

Hao Wu

School of Computer Science, Xi’an Shiyou University

Hualian Tang

School of Microelectronics, Xidian University