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Yukio MITSUYAMA Motoki KIMURA Takao ONOYE Isao SHIRAKAWA
VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.
We propose a new authentication and key establishment (AKE) protocol that can be applied to low-power PDAs in Public Wireless LANs (PWLANs), using two factor authentication and precomputation. This protocol provides mutual authentication, identity privacy, and half forward-secrecy. The computational complexity that the client must perform is just one symmetric key encryption and five hash functions during the runtime of the protocol.