Fingerprints are useful for biometric purposes because of their well known properties of distinctiveness and persistence over time. However, owing to skin conditions or incorrect finger pressure, original fingerprint images always contain noise. Especially, some of them contain useless components, which are often mistaken for the terminations that are an essential minutia of a fingerprint. Mathematical Morphology (MM) is a powerful tool in image processing. In this paper, we propose a linear time algorithm to eliminate impulsive noise and useless components, which employs generalized and ordinary morphological operators based on Euclidean distance transform. There are two contributions. The first is the simple and efficient MM method to eliminate impulsive noise, which can be restricted to a minimum number of pixels. We know the performance of MM is heavily dependent on structuring elements (SEs), but finding an optimal SE is a difficult and nontrivial task. So the second contribution is providing an automatic approach without any experiential parameter for choosing appropriate SEs to eliminate useless components. We have developed a novel algorithm for the binarization of fingerprint images [1]. The information of distance transform values can be obtained directly from the binarization phase. The results show that using this method on fingerprint images with impulsive noise and useless components is faster than existing denoising methods and achieves better quality than earlier methods.

We consider a watermark application to assist in the integrity maintenance and verification of the associated images. There is a great benefit in using WM in the context of authentication since it does not require any additional storage space for supplementary metadata, in contrast with cryptographic signatures, for instance. However there is a fundamental problem in the case of exact authentication: How to embed a signature into a cover message in such a way that it would be possible to restore the watermarked cover image into its original state without any error? There are different approaches to solve this problem. We use the watermarking method consisting of modulo addition of a mark and investigate it in detail. Our contribution lies in investigating different modified techniques of both watermark embedding and detection in order to provide the best reliability of watermark authentication. The simulation results for different types of embedders and detectors in combination with the pictures of watermarked images are given.

In this paper, we define a stopping set of turbo codes with the iterative decoding in the binary erasure channel. Based on the stopping set analysis, we study the block and bit erasure probabilities of turbo codes and the performance degradation of the iterative decoding against the maximum-likelihood decoding. The error floor performance of turbo codes with the iterative decoding is dominated by the small stopping sets. The performance degradation of the iterative decoding is negligible in the error floor region, so the error floor performance is asymptotically dominated by the low weight codewords.

A cell search technique utilizing a known postfix for OFDM (orthogonal frequency division multiplexing) cellular systems is described. The known postfix is generated in the time domain by inserting pilots in the frequency domain and plays the role of the cyclic prefix in general OFDM systems. Since it demonstrates good correlation properties, it can be facilitated to synchronize each symbol with an identified postfix. In this paper, two different known postfixes are allocated to each cell. One is used for cell identification and symbol synchronization, which is designed to be different among neighboring cells. The other is used for frame synchronization and is the same for all cells. In the simulation, the cell search is accomplished with a probability greater than 10-3 at -27 dB in a vehicular channel. Even at -30 dB, the cell search probability is greater than 10-2 in a pedestrian channel as well as 10-3 in the AWGN (additive white gaussian noise) channel.

We have developed a promising method for suppressing moisture condensation that prevents insulation failures in surge protectors. By analyzing surge protectors retrieved from the field, we found that electrolytic corrosion had occurred due to the encroachment of sea salt, the application of bias voltages, and the condensation of moisture. To suppress moisture condensation, a key factor in insulation failure, we applied a previously developed humidity-control package containing water-absorbent polymer. We experimentally optimized the design and functionality of the polymer package. We found that sealing the feed-through apertures alone was not enough to suppress moisture inflow and that a relatively large amount of water-absorbent polymer was needed to prevent water condensation in environments with extremely high humidity for extended periods of time. Laboratory experiments and field tests demonstrated that our optimized package minimized humidity fluctuation and thus moisture condensation in surge protectors, thereby preventing insulation failure. Application of this method to installed surge protectors greatly reduced the insulation failure rate.

In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt, +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).

This paper presents an approach to specification-based testing of concurrent programs with representative test sequences generated from Statecharts. Representative test sequences are a subset of all possible interleavings of concurrent events that define the behaviors of a concurrent program. Because a program's correctness may be determined by checking whether a program implemented all behaviors in its specification or not, the program can be regarded as being correct if it can supply an alternative execution that has the same effects as the program's behavior with each representative test sequence. Based on this observation, we employ each representative test sequence as a seed to generate an automaton that accepts its equivalent sequences to reveal the same behavior. In order to effectively test a concurrent program, the automaton such generated accepts all sequences equivalent to the representative test sequence and it is used to control test execution. This paper describes an automated process of generating automata from a Statecharts specification and shows how the proposed approach works on Statecharts specifications through some examples.

In this paper, a practical clock-scheduling engine is introduced. The minimum feasible clock-period is obtained by using a modified Bellman-Ford shortest path algorithm. Then an optimum cost clock-schedule is obtained by using a bipartite matching algorithm. It also provides useful information to circuit synthesis tools. The experiment to a circuit with about 10000 registers and 100000 signal paths shows that a result is obtained within a few minutes. The computation time is almost linear to the circuit size in practice.

Supporting diversified rates for real-time communications will become possible and essential with the rapidly increasing transmission rates provided by the 4th generation (4G) mobile communication systems. In this paper, a novel wireless Quality of Service (QoS) scheme suitable for broadband CDMA packet cellular systems with adaptive modulation coding is proposed and its characteristics are described. The proposed QoS scheme comprises several control factors laid on the MAC and RRC layers, and can be harmonized with IP-QoS. Two important control factors are proposed: radio-condition-aware admission control and resource allocation reflected multistage scheduling. Computer simulations and testbed experiments indicate that by using the radio-condition-aware admission control, stable and guaranteed service can be provided to real-time users regardless of the interference and the variation in the location of the mobile station. Moreover, resource allocation reflected multistage scheduling maintains guaranteed rates for real-time users and provides high resource utilization efficiency for best-effort users. Consequently, by using the proposed wireless QoS scheme, it is possible to provide users with high quality and diversified real-time services, on a packet based radio network for enhanced 3G and beyond.

We consider oscillators consisting of a reactance circuit and a negative resistor. They may happen to have multi-mode oscillations around the anti-resonant frequencies of the reactance circuit. This kind of oscillators can be easily synthesized by setting the resonant and anti-resonant frequencies of the reactance circuits. However, it is not easy to analyze the oscillation phenomena, because they have multiple oscillations whose oscillations depend on the initial guesses. In this paper, we propose a Spice-oriented solution algorithm combining the harmonic balance method with Newton homotopy method that can find out the multiple solutions on the homotopy paths. In our analysis, the determining equations from the harmonic balance method are given by modified equivalent circuit models of "DC," "Cosine" and "Sine" circuits. The modified circuits can be solved by a simulator STC (solution curve tracing circuit), where the multiple oscillations are found by the transient analysis of Spice. Thus, we need not to derive the troublesome circuit equations, nor the mathematical transformations to get the determining equations. It makes the solution algorithms much simpler.

An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.025.33 mm2 with six-metal 90-nm CMOS technology.

We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.

In unidentifiable models, the Bayes estimation has the advantage of generalization performance over the maximum likelihood estimation. However, accurate approximation of the posterior distribution requires huge computational costs. In this paper, we consider an alternative approximation method, which we call a subspace Bayes approach. A subspace Bayes approach is an empirical Bayes approach where a part of the parameters are regarded as hyperparameters. Consequently, in some three-layer models, this approach requires much less computational costs than Markov chain Monte Carlo methods. We show that, in three-layer linear neural networks, a subspace Bayes approach is asymptotically equivalent to a positive-part James-Stein type shrinkage estimation, and theoretically clarify its generalization error and training error. We also discuss the domination over the maximum likelihood estimation and the relation to the variational Bayes approach.

This letter proposes an orthogonal frequency division multiplexing (OFDM) frame synchronization scheme when the guard interval (GI) consists of a zero-padded (ZP) sequence. The frame synchronization method uses the ZP symbol where nothing is transmitted for GI so that the drop in received power can be detected to find the beginning of the frame. Simulations reveal that this method significantly improves synchronization performance of the ZP-OFDM system in a multipath fading channel.

Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.

A new system identification based method has been proposed for accurate estimation of vocal tract parameters. An often encountered problem in using the conventional linear prediction analysis is due to the harmonic structure of the excitation source of voiced speech. This harmonic characteristic is coupled with the estimation of autoregressive (AR) coefficients that results in difficulties in estimating the vocal tract filter. This paper models the effective voice source from the residual obtained through the covariance analysis in the first-pass which is then used as input to the second-pass least-square analysis. A better source-filter separation is thus achieved. The formant frequencies and corresponding bandwidths obtained using the proposed method for synthetic vowels are found to be accurate up to a factor of more than three (in percent) compared to the conventional method. Since the source characteristic is taken into account, local variations due to the positioning of analysis window are reduced significantly. The validity of the proposed method is also examined by inspecting the spectra obtained from natural vowel sounds uttered by high-pitched female speaker.

In this letter, a new formula is proposed for calculating the polarization entropy, based on the least square method. There is no need to calculate the eigenvalues of a covariance matrix as well as to use logarithms of values. So the time for computing the polarization entropy is reduced. Using polarimetric SAR data, the authors validate the effectiveness of the new formula.

One important question for quantum computing is whether a computational gap exists between models that are allowed to use quantum effects and models that are not. Several types of quantum computation models have been proposed, including quantum finite automata and quantum pushdown automata (with a quantum pushdown stack). It has been shown that some quantum computation models are more powerful than their classical counterparts and others are not since quantum computation models are required to obey such restrictions as reversible state transitions. In this paper, we investigate the power of quantum pushdown automata whose stacks are assumed to be implemented as classical devices, and show that they are strictly more powerful than their classical counterparts under the perfect-soundness condition, where perfect-soundness means that an automaton never accepts a word that is not in the language. That is, we show that our model can simulate any probabilistic pushdown automata and also show that there is a non-context-free language which quantum pushdown automata with classical stack operations can recognize with perfect soundness.

This paper presents method that offers the fast and accurate analysis of large-scale periodic array antennas by conjugate-gradient fast Fourier transform (CG-FFT) combined with an equivalent sub-array preconditioner. Method of moments (MoM) is used to discretize the electric field integral equation (EFIE) and form the impedance matrix equation. By properly dividing a large array into equivalent sub-blocks level by level, the impedance matrix becomes a structure of Three-level Block Toeplitz Matrices. The Three-level Block Toeplitz Matrices are further transformed to Circulant Matrix, whose multiplication with a vector can be rapidly implemented by one-dimension (1-D) fast Fourier transform (FFT). Thus, the conjugate-gradient fast Fourier transform (CG-FFT) is successfully applied to the analysis of a large-scale periodic dipole array by speeding up the matrix-vector multiplication in the iterative solver. Furthermore, an equivalent sub-array preconditioner is proposed to combine with the CG-FFT analysis to reduce iterative steps and the whole CPU-time of the iteration. Some numerical results are given to illustrate the high efficiency and accuracy of the present method.

This letter analyzes the performance of statistical cooperative diversity based on space-time block codes (STBC) (Statistical STBC cooperative diversity) considering the effects of quantization and observation noise. Binary quantization is used. The bit error rate (BER) and average mutual information of the statistical STBC cooperative diversity with Alamouti's STBC and two active nodes are derived in the presence of general observation noise. It is shown that the performance of the statistical STBC cooperative diversity depends on the effects of observation noise and the number of cooperating nodes largely. It is also shown how much the communication between sensor nodes or feedback from the fusion center improves the performance of STBC cooperative diversity.