Application-level multicast (ALM) is a novel technology for multipoint applications, such as large scale file distribution, video and audio streaming, and video conferencing. Although many ALM mechanisms or algorithms have been proposed, all the multicast functions have been independently developed and integrated into individual applications. In such a situation, the development of ALM applications includes a lot of redundancy. Our goal is to improve the efficiency of developing ALM applications by reducing the development redundancy and to provide application developers with a middleware on which various ALM applications can be efficiently developed with minimum efforts. To this end, we develop a functional unit oriented ALM middleware, namely RelayCast. RelayCast provides a minimum but fundamental set of functionality as a functional unit, and constructs the basis on which additional and specific functions (i.e. codec, video capture, etc.) for each application are implemented. Some functional units contain several components with different algorithms, and RelayCast meets the requirements of various applications by choosing the appropriate component. In this paper, we propose RelayCast architecture, and present the implementation and experiments of a prototype.

A new channel estimator that does not require a separate frequency offset estimator is proposed. The new algorithm has low complexity and low latency compared to the well-known weighted multi-slot averaging algorithm. The simulation results demonstrate the improved resistance to high Doppler frequency and high frequency offset.

This paper presents a fuzzy optimization based scheduling method for the manufacturing systems with uncertain production capacities. To address the uncertainties efficiently, the fuzzy optimization technique is used in defining the scheduling problem. Based on the symmetric approach of fuzzy optimization and Lagrangian relaxation technique, a practical fuzzy-optimization based algorithm is developed. The computational experiments based on the real factory data demonstrate that the proposed method provides robust scheduling to hedge against uncertainties.

This letter presents a method of finding the optimal quantization stepsize that minimizes quantization loss and maximizes coded BER performance. We define 'Information Error Rate'(IER) and obtain the equation of the modified constraint length (Km) to obtain an upper bound of coded BER performance of a l bit quantized soft decision Viterbi decoder. Using IER and Km, we determine the optimal quantization stepsize of a 2 bit and 3 bit quantized soft decision decoding system in an AWGN channl with respect to SNR, and verify our strategies by simulation results.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

This paper proposes a novel cache architecture for low power consumption, called "Adaptive Way-Predicting Cache (AWP cache)." The AWP cache has multi-operation modes and dynamically adapts the operation mode based on the accuracy of way-prediction results. A confidence counter for way prediction is implemented to each cache set. In order to analyze the effectiveness of the AWP cache, we perform a SRAM design using 0.18 µm CMOS technology and cycle-accurate processor simulations. As the results, for a benchmark program (179.art), it is observed that a performance-aware AWP cache reduces the 49% of performance overhead caused by an original way-predicting cache to 17%. Furthermore, a energy-aware AWP cache achieves 73% of energy reduction, whereas that obtained from the original way-predicting scheme is only 38%, compared to an non-optimized conventional cache. For the consideration of energy-performance efficiency, we see that the energy-aware AWP cache produces better results; the energy-delay product of conventional organization is reduced to only 35% in average which is 6% better than the original way-predicting scheme.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

In this paper, we propose an efficient rate and power allocation scheme for multiuser OFDM systems to minimize the total transmit power under the given QoS requirements. We deduce the optimal solution of transmit power minimization problem and develop a suboptimal algorithm with low complexity based on the theoretical analysis. Because of the avoidance of iterative procedure, it is less complex than the existing schemes. The simulation results show that our proposal outperforms the existing schemes and it is very close to the optimal solution.

Locality in high frequency diffraction is embodied in the Method of Moments (MoM) in view of the method of stationary phase. Local-domain basis functions accompanied with the phase detour, which are not entire domain but are much larger than the segment length in the usual MoM, are newly introduced to enhance the cancellation of mutual coupling over the local-domain; the off-diagonal elements in resultant reaction matrix evanesce rapidly. The Fresnel zone threshold is proposed for simple and effective truncation of the matrix into the sparse band matrix. Numerical examples for the 2-D strip and the 2-D corner reflector demonstrate the feasibility as well as difficulties of the concept; the way mitigating computational load of the MoM in high frequency problems is suggested.

A fully Internet-connected business environment is subject to frequent changes. To ordinary customers, online shopping under such a dynamic environment can be frustrating. We propose a new E-commerce service called the CIGMA to assist online customers under such an environment. The CIGMA provides catalog comparison and purchase mediation services over multiple shopping sites for ordinary online customers. The service is based on up-to-date information by reflecting the frequent changes in catalog information instantaneously. It also matches the desire of online customers for fast response. This paper describes the CIGMA along with its architecture and the implementation of a working prototype.

In conventional OFDM systems, the effect of inter-block-interference (IBI) can be completely removed by inserting sufficient redundant symbols between successive transmission blocks. In this paper, based on the reformulated received block symbols of the discrete multirate filterbanks model, a new transceiver model for the cyclic prefix (CP) OFDM systems is proposed, associated with the oblique projector technique (view as the pre-processor for achieving IBI-free). Consequently, a novel ISI-free receiver with the zero-order FIR zero-forcing (ZF) filterbanks equalizer can be devised, under noise-free environment. For performance comparison the bit-error-rate (BER) is investigated for the cases of noisy and noise-free channels. In all cases, viz., the length of CP is shorter or longer than the order of the channel impulse response, we show that the same BER performance compared with the one suggested in [3] can be achieved, under the same assumptions and conditions. Since a simple cascade configuration of the IBI cancellation using the oblique projector followed by the ISI cancellation using the zero-order FIR ZF filterbanks equalizer can be realized for OFDM systems with sufficient or insufficient CP, the complexity of transceiver design can be reduced.

In this paper, we propose a new method for the electromagnetic fields with inhomogeneous media mixed a positive and negative regions by the combination of improved Fourier series expansion method using the extrapolation method which obtains the correct value of the eigenvalue and eigenvectors for the case of TM wave. Numerical results are given for the power reflection and transmission coefficient, the energy absorption, the electromagnetic fields, and the power flow in the inhomogeneous medium mixed the positive and negative regions including the case when the permittivity profiles touches zero for the TM wave. The results of our method are in good agreement with exact solution which is obtained the modified multilayer approximation method.

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. In addition, the experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method. Our hierarchical approach reduces the runtimes drastically. Although this approach has possibility to generate wider placements than that of the flat approach, the experimental results show that the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach.

In this paper, an efficient equivalence checking method for two C descriptions is described. The equivalence of two C descriptions is proved by symbolic simulation. Symbolic simulation used in this paper can prove the equivalence of all of the variables in the descriptions. However, it takes long time to verify the equivalence of all of the variables if large descriptions are given. Therefore, in order to improve the verification, our method identifies textual differences between descriptions. The identified textual differences are used to reduce the number of equivalence checkings among variables. The proposed method has been implemented in C language and evaluated with several C descriptions.

In this paper, a new algorithm for the optimal training sequence with respect to sequence length in 1-dimensional cluster-based sequence equalizers (1-D CBSE) is presented. The proposed method not only removes the step of random training sequence selection but also shortens the length of the selected training sequences. The superiority of the new method is demonstrated by presenting several simulation results of quadrature phase shift keying (QPSK) signaling schemes and related analyses.

This paper proposes a block-based video encoder employing variable frame skipping (VFS) to improve the video quality in low bit rate channel. The basic idea of VFS mechanism is to decide and skip a suitable, non-fixed number of frames in temporal domain to reduce bit usage. The saved bits can be allocated to enhance the spatial quality of video. In literature, several methods of frame skipping decision have been proposed, but most of them only consider the similarities between neighboring coded frames as the decision criteria. Our proposed method takes into account the reconstruction of the skipped frames using motion-compensated frame interpolation at decoder. The proposed VFS models the reconstructed objective quality of the skipped frame and, therefore, can provide a fast estimate to the frame skipping at encoder. The proposed VFS can determine the suitable frame skipping in real time and provide the encoded video with better spatial-temporal bit allocation.

In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.

This paper proposes a coordinator for workflow management systems (WFMSs). It is a basic module for developing WFMSs. It is also a coordinator to coordinate multiple WFMSs. The coordinator provides functions to facilitate executing workflows and to ensure secure access of workflow information. Facilitating workflow execution is well-known, but ensuring secure access of workflow information is identified as important only recently. Although many models ensure secure workflow information access, they fail to offer the features we need. We thus developed a new model for the control. This paper presents the coordinator its access control model.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.