This paper introduces τk notation to be used to assess test generation complexity of classes of sequential circuits. Using τk notation, we reconsider and restate the time complexity of test generation for existing classes of acyclic sequential circuits. We also introduce a new DFT method called feedback shift register (FSR) scan design technique, which is extended from the scan design technique. Therefore, for a given sequential circuit, the corresponding FSR scan designed circuit has always equal or lower area overhead and test application time than the corresponding scan designed circuit. Furthermore, we identify some new classes of sequential circuits that contain some cyclic sequential circuits, which are τ-equivalent and τ2-bounded. These classes are the l-length-bounded testable circuits, l-length-bounded validity-identifiable circuits, t-time-bounded testable circuits and t-time-bounded validity-identifiable circuits. In addition, we provide two examples of circuits belonging to these classes, namely counter-cycle finite state machine realizations and state-shiftable finite state machine realizations. Instead of using a DFT method, a given sequential circuit described at the finite state machine (FSM) level can be synthesized using another test methodology called synthesis for testability (SFT) into a circuit that belongs to one of the easily testable classes of cyclic sequential circuits.

Although the multiuser detection scheme based on Kalman filtering (K-MUD) proposed by Zhang and Wei, is referred to as a "blind" algorithm, in fact it is not really blind because it is conditioned on perfect knowledge of system parameter, power of the desired user. This paper derives an algorithm to estimate the power of the user of interest, and proposes a completely blind multiuser detection. Computer simulations show that the proposed parameter estimation scheme obtains excellent effect, and that the new detection scheme has nearly the same performance as the K-MUD, there is only slight degradation at very low input signal-to-interference ratios (SIR).

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

This letter presents a method of finding the optimal quantization stepsize that minimizes quantization loss and maximizes coded BER performance. We define 'Information Error Rate'(IER) and obtain the equation of the modified constraint length (Km) to obtain an upper bound of coded BER performance of a l bit quantized soft decision Viterbi decoder. Using IER and Km, we determine the optimal quantization stepsize of a 2 bit and 3 bit quantized soft decision decoding system in an AWGN channl with respect to SNR, and verify our strategies by simulation results.

In order to eliminate the co-channel and multi-path interference of quasi-synchronous code division multiple access (QS-CDMA) systems, spreading sequences with low or zero correlation zone (LCZ or ZCZ) can be used. The significance of LCZ/ZCZ to QS-CDMA systems is that, even there are relative delays between the transmitted spreading sequences due to the inaccurate access synchronization and the multipath propagation, the orthogonality (or quasi-orthogonality) between the transmitted signals can still be maintained, as long as the relative delay does not exceed certain limit. In this paper, several lower bounds on the aperiodic autocorrelation and crosscorrelation of binary LCZ/ZCZ sequence set with respect to the family size, sequence length and the aperiodic low or zero correlation zone, are derived. The results show that the new bounds are tighter than previous bounds for the LCZ/ZCZ sequences.

There are several optimization techniques available for improving rendering speed of direct volume rendering. An acceleration method using the hierarchical min-max map requires little preprocessing and data storage while preserving image quality. However, this method introduces computational overhead because of unnecessary comparison and level shift between blocks. In this paper, we propose an efficient space-leaping method using optimal-sized blocks. To determine the size of blocks, our method partitions an image plane into several uniform grids and computes the minimum and the maximum depth values for each grid. We acquire optimal block sets suitable for individual rays from these values. Experimental results show that our method reduces rendering time when compared with the previous min-max octree method.

In [1], an algorithm based on phase variations of received pilot symbols was proposed to estimate one of the most important channel parameters, maximum Doppler shift, fd. However, AWGN (Additive white gauss noise) will cause large estimation error in some cases. In order to analyze the influence of noise, we extended the phase probability density function (pdf) in [1] to the scenario with both fading and AWGN, then the estimation error is characterized in closed-form expression. By this error expression, we found that power control will affect the estimator of [1] and we proposed a modification method based on SNR estimation to obtain accurate Doppler shift estimation in moderate low SNRs (signal-to-noise ratio). Simulation results show high accuracy in wide range of velocities and SNRs.

In conventional OFDM systems, the effect of inter-block-interference (IBI) can be completely removed by inserting sufficient redundant symbols between successive transmission blocks. In this paper, based on the reformulated received block symbols of the discrete multirate filterbanks model, a new transceiver model for the cyclic prefix (CP) OFDM systems is proposed, associated with the oblique projector technique (view as the pre-processor for achieving IBI-free). Consequently, a novel ISI-free receiver with the zero-order FIR zero-forcing (ZF) filterbanks equalizer can be devised, under noise-free environment. For performance comparison the bit-error-rate (BER) is investigated for the cases of noisy and noise-free channels. In all cases, viz., the length of CP is shorter or longer than the order of the channel impulse response, we show that the same BER performance compared with the one suggested in [3] can be achieved, under the same assumptions and conditions. Since a simple cascade configuration of the IBI cancellation using the oblique projector followed by the ISI cancellation using the zero-order FIR ZF filterbanks equalizer can be realized for OFDM systems with sufficient or insufficient CP, the complexity of transceiver design can be reduced.

Locality in high frequency diffraction is embodied in the Method of Moments (MoM) in view of the method of stationary phase. Local-domain basis functions accompanied with the phase detour, which are not entire domain but are much larger than the segment length in the usual MoM, are newly introduced to enhance the cancellation of mutual coupling over the local-domain; the off-diagonal elements in resultant reaction matrix evanesce rapidly. The Fresnel zone threshold is proposed for simple and effective truncation of the matrix into the sparse band matrix. Numerical examples for the 2-D strip and the 2-D corner reflector demonstrate the feasibility as well as difficulties of the concept; the way mitigating computational load of the MoM in high frequency problems is suggested.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

NAT-PT and DSTM are becoming more widespread as de-facto standards for IPv6 dominant network deployment. But few researchers have empirically evaluated their performance aspects. In this paper, we compared the performance of NAT-PT and DSTM with IPv4-only and IPv6-only networks on user applications using metrics such as throughput, CPU utilization, round-trip time, and connect/request/response transaction rate.

This paper proposes a block-based video encoder employing variable frame skipping (VFS) to improve the video quality in low bit rate channel. The basic idea of VFS mechanism is to decide and skip a suitable, non-fixed number of frames in temporal domain to reduce bit usage. The saved bits can be allocated to enhance the spatial quality of video. In literature, several methods of frame skipping decision have been proposed, but most of them only consider the similarities between neighboring coded frames as the decision criteria. Our proposed method takes into account the reconstruction of the skipped frames using motion-compensated frame interpolation at decoder. The proposed VFS models the reconstructed objective quality of the skipped frame and, therefore, can provide a fast estimate to the frame skipping at encoder. The proposed VFS can determine the suitable frame skipping in real time and provide the encoded video with better spatial-temporal bit allocation.

In this paper, we propose a new method for the electromagnetic fields with inhomogeneous media mixed a positive and negative regions by the combination of improved Fourier series expansion method using the extrapolation method which obtains the correct value of the eigenvalue and eigenvectors for the case of TM wave. Numerical results are given for the power reflection and transmission coefficient, the energy absorption, the electromagnetic fields, and the power flow in the inhomogeneous medium mixed the positive and negative regions including the case when the permittivity profiles touches zero for the TM wave. The results of our method are in good agreement with exact solution which is obtained the modified multilayer approximation method.

A new channel estimator that does not require a separate frequency offset estimator is proposed. The new algorithm has low complexity and low latency compared to the well-known weighted multi-slot averaging algorithm. The simulation results demonstrate the improved resistance to high Doppler frequency and high frequency offset.

This paper proposes a novel cache architecture for low power consumption, called "Adaptive Way-Predicting Cache (AWP cache)." The AWP cache has multi-operation modes and dynamically adapts the operation mode based on the accuracy of way-prediction results. A confidence counter for way prediction is implemented to each cache set. In order to analyze the effectiveness of the AWP cache, we perform a SRAM design using 0.18 µm CMOS technology and cycle-accurate processor simulations. As the results, for a benchmark program (179.art), it is observed that a performance-aware AWP cache reduces the 49% of performance overhead caused by an original way-predicting cache to 17%. Furthermore, a energy-aware AWP cache achieves 73% of energy reduction, whereas that obtained from the original way-predicting scheme is only 38%, compared to an non-optimized conventional cache. For the consideration of energy-performance efficiency, we see that the energy-aware AWP cache produces better results; the energy-delay product of conventional organization is reduced to only 35% in average which is 6% better than the original way-predicting scheme.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

Fixed polarity Reed-Muller expressions (FPRMs) exhibit several useful properties that make them suitable for many practical applications. This paper presents an exact minimization algorithm for FPRMs for incompletely specified functions. For an n-variable function with α unspecified minterms there are 2n+α distinct FPRMs, and a minimum FPRM is one with the fewest product terms. To find a minimum FPRM the algorithm requires to determine an assignment of the incompletely specified minterms. This is accomplished by using the concept of integer-valued functions in conjunction with an extended truth vector and a weight vector. The vectors help formulate the problem as an assignment of the variables of integer-valued functions, which are then efficiently manipulated by using multi-terminal binary decision diagrams for finding an assignment of the unspecified minterms. The effectiveness of the algorithm is demonstrated through experimental results for code converters, adders, and randomly generated functions.