In this letter, we derive a very accurate closed-form approximate formula for the average achievable rate of stacked orthogonal space-time block code (OSTBC) in Rayleigh fading channels. Some simulations are performed to demonstrate that the derived formula shows better agreement with Monte-Carlo simulation results than the existing closed-form approximate expressions.

We propose Adaptive Resource Allocation for the Partial Block MC-CDMA (ARA-PB/MC-CDMA) system. The ARA-PB/MC-CDMA system aims to improve total throughput performance and frequency efficiency across various channel conditions. It adaptively changes the number of blocks to improve the throughput performance and frequency efficiency according to the Signal to Interference Ratio (SIR). Therefore, the proposed system supports various Quality of Service (QoS) requirements for various SIR values.

Mobile Ad Hoc Networks (MANETs) are temporal and infrastructure-independent wireless networks that consist of mobile nodes. For instance, a MANET can be used as an emergent network for communication among people when a disaster occurred. Since there is no central server in the network, each node has to find out its desired information (objects) by itself. Constructing a mobile Peer-to-Peer (P2P) network over the MANET can support the object search. Some researchers proposed construction schemes of mobile P2P networks, such as Ekta and MADPastry. They integrated DHT-based application-layer routing and network-layer routing to increase search efficiency. Furthermore, MADPastry proposed a clustering method which groups the overlay nodes according to their physical distance. However, it has also been pointed out that the search efficiency deteriorates in highly dynamic environments where nodes quickly move around. In this paper, we focus on route disappearances in the network layer which cause the deterioration of search efficiency. We describe the detail of this problem and evaluate quantitatively it through simulation experiments. We extend MADPastry by introducing a method sharing objects among nodes in a cluster. Through simulation experiments, we show that the proposed method can achieve up to 2.5 times larger success rate of object search than MADPastry.

Reversal complexity has been studied as a fundamental computational resource along with time and space complexity. We revisit it by contrasting with access complexity which we introduce in this study. First, we study the structure of space bounded reversal and access complexity classes. We characterize the complexity classes L, P and PSPACE in terms of space bounded reversal and access complexity classes. We also show that the difference between polynomial space bounded reversal and access complexity is related with the L versus P problem. Moreover, we introduce a theory of memory access patterns, which is an abstracted structure of the order of memory accesses during a random access computation, and extend the notion of reversal and access complexity for general random access computational models. Then, we give probabilistic analyses of reversal and access complexity for almost all memory access patterns. In particular, we prove that almost all memory access patterns have ω(log n) reversal complexity while all languages in L are computable within O(log n) reversal complexity.

Time-resolved microscopic optical second harmonic generation (TRM-SHG) imaging measurement revealed quantitatively the potential drop at the electrode contact of pentacene field effect transistors (FET). An activation of the SH signal at the edge of Ag-source electrode indicates the presence of large potential drop at pentacene-Ag contact during device operation, whereas negligible potential drop was observed at pentacene-Au contact. These findings agree with the injection characteristics of electrodes owing to the relationship between the work function of the metal and the HOMO level of pentacene.

To evaluate frequency-domain interference between orthogonally intersecting stripline geometries, a lumped mutual capacitance was incorporated into a circuit model, and then a simplified circuit was proposed in the previous paper. The circuit model was approximated from an investigation of the distribution of mutual capacitance but it has remained how the capacitance is approximated. In this paper, a technique using an error function is proposed for the problem. Then, the time-domain response in an analytical expression is studied using the simplified circuit model in a Laplace transformation to make the mechanism clear. Comparing the experimental and the computed results verifies the proposed models.

In a multi-user orthogonal frequency division multiplexing (OFDM) system, efficient resource allocation is required to provide service to more users. In this letter, we propose an improved subcarrier allocation algorithm that can increase the spectral efficiency and the number of total transmission bits even if the number of users is too large. The proposed algorithm is divided into two stages. In the first stage, a group of users who are eligible for services is determined by using the bit error rate (BER), the users' minimum data rate requirement, and channel information. In the second stage, subcarriers are first allocated to the users on the basis of channel state, and then the reallocation is performed so that resource waste is minimized. We show that the proposed algorithm outperforms the conventional one on the basis of outage probability, spectral efficiency, and the number of total transmission bits through a computer simulation.

Nucleic acid sensor based on polyaniline has been fabricated by covalently immobilizing double stranded calf thymus (dsCT) DNA onto perchlorate (ClO- 4) doped polyaniline (PANI) film deposited onto indium-tin-oxide (ITO) glass plate using 1-(3-(dimethylamino) propyl)-3-ethylcarbodiimide hydrochloride (EDC)/N-hydroxyl succinimide (NHS) chemistry. These dsCT-DNA-PANI/ITO and PANI/ITO electrodes have been characterized using square wave voltammetry, electrochemical impedance, and Fourier-transform-infra-red (FTIR) measurements. This disposable dsCT-DNA-PANI/ITO bioelectrode is stable for about four months, can be used to detect arsenic trioxide (0.1 ppm) in 30 s.

In real-time data-dominated communication and multimedia processing applications, a multi-layer memory hierarchy is typically used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller on-chip memories rather than from large background memories. This paper focuses on the reduction of the dynamic energy consumption in the memory subsystem of multidimensional signal processing systems, starting from the high-level algorithmic specification of the application. The paper presents a formal model which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings of dynamic energy from 40% to over 70% relative to the energy used in the case of flat memory designs.

This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.

In this paper, an alternative approach is presented, to design equalizers (or matching networks) with commensurate (or equal length) transmission lines. The new method automatically yields the matching network topology with characteristic impedances of the commensurate lines. In the implementation process of the new technique first, the driving point impedance data of the matching network is generated by tracing a pre-selected transducer power gain shape, without optimization. Then, it is modelled as a realizable bounded-real input reflection coefficient in Richard domain, which in turn yields the desired equalizer topology with line characteristic impedances. This process results in an excellent initial design for the commercially available computer aided design (CAD) packages to generate final circuit layout for fabrication. An example is given to illustrate the utilization of the new method. It is expected that the proposed design technique is employed as a front-end, to commercially available computer aided design (CAD) packages which generate the actual equalizer circuit layout with physical dimensions for mass production.

A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.

Intra coding in H.264/AVC has significantly enhanced video compression efficiency. However, computation complexity increases by the rate-distortion (RD) based mode decision. This paper proposes a novel fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A novel edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce the number of intra 44 candidate modes from 9 to an average of 2.50. VLSI architecture of intra mode decision module is designed with TSMC 0.18 µm CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1k NAND gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30 fps real time encoder.

Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.

With the popularity of BitTorrent-like P2P applications, improving its performance has been an active research area. Super-seeding, a special upload policy for the initial seeder, improves the efficiency in producing multiple seeds and reduces the uploading bytes of content initiators, thus being highly expected as a promising solution for improving downloading performance while decreasing uploading cost. However, the overall impacts of super seeding upon BitTorrent performance remain a question and have not been analyzed so far in literature. In this paper, we present an analytical and experimental study over the performance of super-seeding scheme. We attempt to answer the following questions: whether and how much super-seeding saves uploading cost, whether the overall downloading time is decreased by super-seeding, and in which circumstances super-seeding performs worse. Based on the seeding process, our analytical study gives formulas on the new piece distribution time, average downloading time and minimum distribution time for heterogeneous P2P file distribution system with super-seeding. Robust evidence supporting the use (or not) of super-seeding is given based on our worldwide Internet experiments over wide distribution of 250 PlanetLab nodes. With a well-designed experimental scenario, we study the overall download time and upload cost of super seeding scheme under varying seed bandwidth and peer behavior. Results show that super-seeding can save an upload ratio of 20% and does help speeding up swarms in certain modes. Tentative conclusions about the effectiveness of super-seeding and its optimal working circumstances are given with inside mechanism analyzed and negative factor identified. Our work not only provides reference for the potential adoption of super-seeding in BitTorrent and other P2P applications, but also much insights for the tussle of enhancing of Quality of Experience (QoE) and saving cost for a large-scale BitTorrent-like P2P commercial application.

We have developed novel humidity and gas detector system using quartz crystal oscillators (QCO) deposited with cellulose Langmuir-Blodgett (LB) films. We have realized stable humidity detection by the LB-based QCO sensor for extremely high humidity subsequent to the water dipping condition. Also, specific gaseous molecules such as alcohol could have been sensitively detected.

Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.

A transducer with a wide step from a post-wall waveguide to a hollow waveguide width is proposed which is tolerant against the aperture offset. The modes in the step width of about 1.50 wavelengths are stable for the aperture offset and the fields are not so perturbed while in the conventional stepped structure with step width of about 1.00 wavelength, the higher evanescent mode of TE30 is excessively enhanced by the aperture offset. The operation of the transducer with the wider step is robust for the fabrication errors in the millimeter wave band. It is also suggested that the anti-symmetrical TE20 mode which is excited only by non-zero offset or the misalignment of the aperture exists in both structures and can not be the dominant factor for the improvement. The transducers are designed and fabricated at 61.25 GHz using PTFE substrate with glass fiber of εr=2.17. The bandwidth for the reflection lower than -15 dB is almost unchanged (6.30-6.60 GHz) for the offset from -0.2 mm to 0.2 mm, while it is degraded in the conventional stepped structure, from 7.65 GHz for no offset to 3.30-5.70 GHz for the same range of the offset.

In this paper, we propose an Adaptive Stochastic Collocation Method for block-based Statistical Static Timing Analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on Homogeneous Chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using Sparse Grid technique, the proposed method has 10x improvements in the accuracy while using the same order of computation time. The proposed algorithm also shows great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100x speeds up.

Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.