This letter presents a new mathematical expression for the excess mean-square error (EMSE) of the affine projection (AP) algorithm. The proposed expression explicitly shows the proportional relationship between the EMSE and the condition number of the input signals.

This paper investigates the performance of multiple monopole antennas mounted on a card-type terminal, which is expected to be used in the systems beyond 3 G, based on the calculated and measured radiation patterns for the 2.0 GHz. We characterize the feasible performance of quarter-wavelength monopole antennas mounted on a card-type terminal in a multiple antenna configuration with narrow element spacing of less than a half-wavelength assuming that the antennas used must satisfy the space restrictions of the mobile terminal. Performance figures of merit for the multiple antenna performance include the beamforming gain, correlation coefficient, and MIMO channel capacity. Furthermore, we investigate the influence of a finite ground plane on the characteristics of multiple monopole antennas using a typical antenna configuration comprising a simple finite ground plane and multiple monopole antennas to discuss the fundamental characteristics.

Sensor node localization is an important issue in wireless sensor networks (WSNs) due to the dynamic nature of sensor deployment. Generally, in wireless sensor network localization, the absolute positions of certain anchor nodes are required based on the use of global positioning systems, then all the other nodes are approximately localized using various algorithms based on a coordinate system of the anchors. This paper proposes a neighbor position-based localization algorithm (NPLA) that can greatly enhance the positioning accuracy when compared with current overlapping connectivity localization algorithms that attempt to use the observation of connectivity to a set of anchors to determine a node's position. The proposed method localizes the sensor nodes using both the anchors' positions and neighbor node information. However, unlike existing overlapping-based methods, the proposed NPLA does not assume the same radio transmission range. A simulation study is used to demonstrate the positioning accuracy of the proposed method with different anchor and sensor node densities.

In this paper, we consider a collision detection problem of spheres which asks to detect all pairs of colliding spheres in a set of n spheres located in d-dimensional space. We propose a collision detection algorithm for spheres based on slab partitioning technique and a plane sweep method. We derive a theoretical upper bound on the time complexity of the algorithm. Our bound tells that if both the dimension and the maximum ratio of radii of two spheres are bounded, then our algorithm runs in O(n log n + K) time with O(n + K) space, where K denotes the number of pairs of colliding spheres.

In this paper, we shall describe about a fuzzy estimation theory based on the concept of set-valued operators, suitable for available operation of extremely complicated large-scale network systems. Fundamental conditions for availability of system behaviors of such network systems are clarified in a form of β-level fixed point theorem for system of fuzzy-set-valued operators. Here, the proof of this theorem is accomplished in a weak topology introduced into the Banach space.

Motivated by the recent works of coded cooperation this letter presents a composite signal structure based coded cooperation technique. Our proposed protocol performs well in both slow and fast fading whereas, conventional coded cooperation is ineffective in fast fading. We develop the bounds on BER and FER of our proposal. Simulations confirm our developed bound and shows that the proposed coded cooperation protocol outperforms direct transmission in both fast and slow fading environments.

A rectangular drawing is a plane drawing in which every face is a rectangle. In this paper we give a simple encoding scheme for rectangular drawings. Given a rectangular drawing R with maximum degree 3, our scheme encodes R with m + o(n) bits where n is the number of vertices of R and m is the number of edges of R. Also we give an algorithm to supports a rich set of queries, including adjacency and degree queries on the faces, in constant time.

In Shamir's (k,n)-threshold secret sharing scheme (threshold scheme)[1], a heavy computational cost is required to make n shares and recover the secret from k shares. As a solution to this problem, several fast threshold schemes have been proposed. However, there is no fast ideal (k,n)-threshold scheme, where k and n are arbitrary. This paper proposes a new fast (k,n)-threshold scheme which uses just EXCLUSIVE-OR(XOR) operations to make n shares and recover the secret from k shares. We prove that every combination of k or more participants can recover the secret, but every group of less than k participants cannot obtain any information about the secret in the proposed scheme. Moreover, the proposed scheme is an ideal secret sharing scheme similar to Shamir's scheme, in which every bit-size of shares equals that of the secret. We also evaluate the efficiency of the scheme, and show that our scheme realizes operations that are much faster than Shamir's.

Given a simple graph G with n vertices, m edges and k connected components. The spanning forest problem is to find a spanning tree for each connected component of G. This problem has applications to the electrical power demand problem, computer network design, circuit analysis, etc. An optimal parallel algorithm for finding a spanning tree on the trapezoid graph is given by Bera et al., it takes O(log n) time with O(n/log n) processors on the EREW (Exclusive-Read Exclusive-Write) PRAM. Bera et al.'s algorithm is very simple and elegant. Moreover, it can correctly construct a spanning tree when the graph is connected. However, their algorithm can not accept a disconnected graph as an input. Applying their algorithm to a disconnected graph, Concurrent-Write occurs once for each connected component, thus this can not be achieved on EREW PRAM. In this paper we present an O(log n) time parallel algorithm with O(n/log n) processors for constructing a spanning forest on trapezoid graph G on EREW PRAM even if G is a disconnected graph.

Shared-Memory Optical Packet (SMOP) switch architecture is very promising for significantly reducing the amount of required optical memory, which is typically constructed from fiber delay lines (FDLs). The current reservation-based scheduling algorithms for SMOP switches can effectively utilize the FDLs and achieve a low packet loss rate by simply reserving the departure time for each arrival packet. It is notable, however, that such a simple scheduling scheme may introduce a significant packet out of order problem. In this paper, we first identify the two main sources of packet out of order problem in the current reservation-based SMOP switches. We then show that by introducing a "last-timestamp" variable and modifying the corresponding FDLs arrangement as well as the scheduling process in the current reservation-based SMOP switches, it is possible to keep packets in-sequence while still maintaining a similar delay and packet loss performance as the previous design. Finally, we further extend our work to support the variable-length burst switching.

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.

The multi-process execution in dynamically reconfigurable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.

Simulation and fabrication results on back-illuminated 4-channel photodiode (PD) array with a self-aligned micro ball lens are described. The channel pitch and diameter of each photosensitive area are 250 µm and 40 µm, respectively. Measured photocurrent is 1.92 times larger than that without a lens. Alignment tolerance between the single mode fiber (SMF) optical axis and the photodiode is improved from 21.2 µm to 42.7 µm. Moreover, the separation tolerance between the fiber and the lens is 210.5 µm. These large tolerances agree with simulation results, demonstrating that the device configuration is suitable for receivers for multi-channel inter-connection. Frequency response and inter-channel cross talk are also discussed.

This paper introduces multiple view geometry under projective projection from four-dimensional space to two-dimensional space which can represent multiple view geometry under the projection of space-time. We show the multifocal tensors defined under space-time projective projection can be derived from non-rigid object motions viewed from multiple cameras with arbitrary translational motions, and they are practical for generating images of non-rigid object motions viewed from cameras with arbitrary translational motions. The method is tested in real image sequences.

In this paper, we introduce new compression function design principles supporting variable output lengths (multiples of size n). They are based on a function or block cipher with an n-bit output size. In the case of the compression function with a(t+1)n-bit output size, in the random oracle and ideal cipher models, their maximum advantages from the perspective of collision resistance are . In the case of t=1, the advantage is near-optimal. In the case of t>1, the advantage is optimal.

A Lyapunov-based recurrent neural networks unified power flow controller (UPFC) is developed for improving transient stability of power systems. First, a simple UPFC dynamical model, composed of a controllable shunt susceptance on the shunt side and an ideal complex transformer on the series side, is utilized to analyze UPFC dynamical characteristics. Secondly, we study the control configuration of the UPFC with two major blocks: the primary control, and the supplementary control. The primary control is implemented by standard PI techniques when the power system is operated in a normal condition. The supplementary control will be effective only when the power system is subjected by large disturbances. We propose a new Lyapunov-based UPFC controller of the classical single-machine-infinite-bus system for damping enhancement. In order to consider more complicated detailed generator models, we also propose a Lyapunov-based adaptive recurrent neural network controller to deal with such model uncertainties. This controller can be treated as neural network approximations of Lyapunov control actions. In addition, this controller also provides online learning ability to adjust the corresponding weights with the back propagation algorithm built in the hidden layer. The proposed control scheme has been tested on two simple power systems. Simulation results demonstrate that the proposed control strategy is very effective for suppressing power swing even under severe system conditions.

For RSA, May showed a deterministic polynomial time equivalence of computing d to factoring N(=pq). On the other hand, Takagi showed a variant of RSA such that the decryption algorithm is faster than the standard RSA, where N=prq while ed=1 mod(p-1)(q-1). In this paper, we show that a deterministic polynomial time equivalence also holds in this variant. The coefficient matrix T to which LLL algorithm is applied is no longer lower triangular, and hence we develop a new technique to overcome this problem.

This paper describes the matrix order reduction method by the nodal analysis formulation and the application of relaxation-based simulation technique to interconnect and plane networks. First, the characteristics of the power/ground plane networks are considered. Next, the formulation of the plane network by nodal analysis (NA) method is suggested. Furthermore, application and estimation results of the relaxation-based numerical analyses are shown. Finally, it is confirmed that the relaxation-based methods improved by the suggested formulation are much more efficient than the conventional direct-based methods.

This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

In this letter, a decentralized scatternet formation algorithm called Bluelayer is proposed. First, Bluelayer uses a designated root to construct a tree-shaped subnet and propagates an integer variable k1 called counter limit as well as a constant k in its downstream direction to determine new roots. Then each new root asks its upstream master to start a return connection procedure to convert the tree-shaped subnet into a web-shaped subnet for its immediate upstream root. At the same time, each new root repeats the same procedure as the root to build its own subnet until the whole scatternet is formed. Simulation results show that Bluelayer achieves good network scalability and generates an efficient scatternet configuration for various sizes of Bluetooth ad hoc network.