In this paper, we propose new external context features for the semantic classification of bio-entities. In the previous approaches, the words located on the left or the right context of bio-entities are frequently used as the external context features. However, in our prior experiments, the external contexts in a flat representation did not improve the performance. In this study, we incorporate predicate-argument features into training the ME-based classifier. Through parsing and argument identification, we recognize biomedical verbs that have argument relations with the constituents including a bio-entity, and then use the predicate-argument structures as the external context features. The extraction of predicate-argument features can be done by performing two identification tasks: the biomedically salient word identification which determines whether a word is a biomedically salient word or not, and the target verb identification which identifies biomedical verbs that have argument relations with the constituents including a bio-entity. Experiments show that the performance of semantic classification in the bio domain can be improved by utilizing such predicate-argument features.

This paper presents a design of an asynchronous peer-to-peer half-duplex/full-duplex-selectable data-transfer system on-chip interconnected. The data-transfer method between channels is based on a 1-phase signaling scheme realized by using multiple-valued current-mode (MVCM) circuits and encoding, which performs high-speed communication. A data transmission is selectable by adding a mode-detection circuit that observes data-transmission modes; full-duplex, half-duplex and standby modes. Especially, since current sources are completely cut off during the standby mode, the power dissipation can be greatly reduced. Moreover, both half-duplex and full-duplex communication can be realized by sharing a common circuit except a signal-level conversion circuit. The proposed interface is implemented using 0.18-µm CMOS, and its performance improvement is discussed in comparison with those of the other ordinary asynchronous methods.

One of the approaches to improve program understanding is to extract what kinds of design pattern are used in existing object-oriented software. This paper proposes a technique for efficiently and accurately detecting occurrences of design patterns included in source codes. We use both static and dynamic analyses to achieve the detection with high accuracy. Moreover, to reduce computation and maintenance costs, detection conditions are hierarchically specified based on Pree's meta patterns as common structures of design patterns. The usage of Prolog to represent the detection conditions enables us to easily add and modify them. Finally, we have implemented an automated tool as an Eclipse plug-in and conducted experiments with Java programs. The experimental results show the effectiveness of our approach.

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18-µm CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity and low power consumption.

Because motion capture system enabled us to capture a number of human motions, the demand for a method to easily browse the captured motion database has been increasing. In this paper, we propose a method to generate simple visual outlines of motion clips, for the purpose of efficient motion data browsing. Our method unfolds a motion clip into a 2D stripe of keyframes along a timeline that is based on semantic keyframe extraction and the best view point selection for each keyframes. With our visualization, timing and order of actions in the motions are clearly visible and the contents of multiple motions are easily comparable. In addition, because our method is applicable for a wide variety of motions, it can generate outlines for a large amount of motions fully automatically.

This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.

A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

Binary search tree and framed ALOHA algorithms are commonly adopted to solve the anti-collision problem in RFID systems. In this letter, the read efficiency of these two anti-collision algorithms is compared through computer simulations. Simulation results indicate the framed ALOHA algorithm requires less total read time than the binary search tree algorithm. The initial frame length strongly affects the uplink throughput for the framed ALOHA algorithm.

Orthogonal frequency-division multiplexing (OFDM) systems often use a cyclic prefix (CP) to simplify the equalization design at the cost of bandwidth efficiency. To increase the bandwidth efficiency, we study the blind equalization with linear smoothing [1] for single-input multiple-output (SIMO) OFDM systems without CP insertion in this paper. Due to the block Toeplitz structure of channel matrix, the block matrix scheme is applied to the linear smoothing channel estimation, which equivalently increases the number of sample vectors and thus reduces the perturbation of sample autocorrelation matrix. Compared with the linear smoothing and subspace methods, the proposed block linear smoothing requires the lowest computational complexity. Computer simulations show that the block linear smoothing yields a channel estimation error smaller than that from linear smoothing, and close to that of the subspace method. Evaluating by the minimum mean-square error (MMSE) equalizer, the block linear smoothing and subspace methods have nearly the same bit-error-rates (BERs).

A packet detection method for zero-padded orthogonal frequency division multiplexing (OFDM) transmission is presented. The proposed algorithm effectively conducts packet detection by employing both an M-sample time delayed cross correlation value, and a received signal power calculated by using the received input samples corresponding to the zero padding (ZP) intervals or less.

This paper shows a necessary condition for type- and Gauss period normal bases in Fpm to be the same normal basis by using their traces.

The problem of joint orthogonal precoding and user scheduling in a multi-user multi-input multi-output (MU-MIMO) downlink system is considered. Based on the theoretics of subspace and vector projection, a novel orthogonal precoding matrix is designed to achieve high sum-rate capacity with low to moderate number of active users and in low SNR regions. With respect to sum-rate capacity, numerical simulations show that the proposed algorithm outperforms the zero-forcing beam-forming (ZFBF) and linear orthogonal beam-forming (OLBF).

Fair queueing is a service scheduling discipline to pursue the fairness among users in packet communication networks. Many fair queueing algorithms, however, have problems of computational overhead since the central scheduler has to maintain a certain performance counter for each flow of user packets based on the global virtual time. Moreover, they are not suitable for wireless networks with high probability of input channel errors due to the lack or complexity in the compensation mechanism for the recovery from the error state. In this paper, we propose a new, computationally efficient, distributed fair queueing scheme, which we call Channel-Aware Throughput Fair Queueing (CATFQ), that is applicable to both wired and wireless packet networks. In our CATFQ scheme, each flow is equipped with a counter that measures the weighted throughput achievement while it has a backlog of packets. At the end of every service to a packet, the scheduler simply selects a flow with the minimum counter value as the one from which a packet is served next. We show that the difference between any two throughput counters is bounded. Our scheme significantly reduces the scheduler's computational overhead and guarantees fair throughput for all flows. For wireless networks with error-prone channels, the service chance lost in bad channel condition is compensated quickly as the channel recovers. Our scheme suppresses the service for leading flows, brings short-term fairness for flows without channel errors, and achieves long-term fairness for all flows. These merits are verified by simulation.

The visual inspection of defects in products is heavily dependent on human experience and instinct. In this situation, it is difficult to reduce the production costs and to shorten the inspection time and hence the total process time. Consequently people involved in this area desire an automatic inspection system. In this paper, we propose a hardware neural network, which is expected to provide high-speed operation for automatic inspection of products. Since neural networks can learn, this is a suitable method for self-adjustment of criteria for classification. To achieve high-speed operation, we use parallel and pipelining techniques. Furthermore, we use a piecewise linear function instead of a conventional activation function in order to save hardware resources. Consequently, our proposed hardware neural network achieved 6GCPS and 2GCUPS, which in our test sample proved to be sufficiently fast.

Previous approaches for modeling Intrusion Detection System (IDS) have been on twofold: improving detection model(s) in terms of (i) feature selection of audit data through wrapper and filter methods and (ii) parameters optimization of detection model design, based on classification, clustering algorithms, etc. In this paper, we present three approaches to model IDS in the context of feature selection and parameters optimization: First, we present Fusion of Genetic Algorithm (GA) and Support Vector Machines (SVM) (FuGAS), which employs combinations of GA and SVM through genetic operation and it is capable of building an optimal detection model with only selected important features and optimal parameters value. Second, we present Correlation-based Hybrid Feature Selection (CoHyFS), which utilizes a filter method in conjunction of GA for feature selection in order to reduce long training time. Third, we present Simultaneous Intrinsic Model Identification (SIMI), which adopts Random Forest (RF) and shows better intrusion detection rates and feature selection results, along with no additional computational overheads. We show the experimental results and analysis of three approaches on KDD 1999 intrusion detection datasets.

Two simple but useful methods, called the deep learning methods, for making multilayer neural networks tolerant to multiple link-weight and neuron-output faults, are proposed. The methods make the output errors in learning phase smaller than those in practical use. The abilities of fault-tolerance of the multilayer neural networks in practical use, are analyzed in the relationship between the output errors in learning phase and in practical use. The analytical result shows that the multilayer neural networks have complete (100%) fault-tolerance to multiple weight-and-neuron faults in practical use. The simulation results concerning the rate of successful learnings, the ability of fault-tolerance, and the learning time, are also shown.

Further development of a network based on the Inverse Function Delayed (ID) model which can recall temporal sequences of patterns, is proposed. Additional advantage is taken of the negative resistance region of the ID model and its hysteretic properties by widening the negative resistance region and letting the output of the ID neuron be almost instant. Calling this neuron limit ID neuron, a model with limit ID neurons connected pairwise with conventional neurons enlarges the storage capacity and increases it even further by using a weightmatrix that is calculated to guarantee the storage after transforming the sequence of patterns into a linear separation problem. The network's tolerance, or the model's ability to recall a sequence, starting in a pattern with initial distortion is also investigated and by choosing a suitable value for the output delay of the conventional neuron, the distortion is gradually reduced and finally vanishes.

This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade (PLK) algorithm. It features a smaller chip area, higher pixel rate, and higher accuracy than conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original PLK algorithm improve the optical-flow accuracy, and reduce the processor hardware cost. Furthermore, window interleaving and window overlap methods reduces the necessary clock frequency of the processor by 70%, allowing low-power characteristics. We first verified the PLK algorithm and architecture with a proto-typed FPGA implementation. Then, we designed a VLSI processor that can handle a VGA 30-fps image sequence at a clock frequency of 332 MHz. The core size and power consumption are estimated at 3.503.00 mm2 and 600 mW, respectively, in a 90-nm process technology.

A design method is proposed for a low-profile dual-shaped reflector antenna for the mobile satellite communications. The antenna is required to be low-profile because of mount restrictions. However, reduction of its height generally causes degradation of antenna performance. Firstly, an initial low-profile reflector antenna with an elliptical aperture is designed by using Geometrical Optics (GO) shaping. Then a Physical Optics (PO) shaping technique is applied to optimize the gain and sidelobes including mitigation of undesired scattering. The developed design method provides highly accurate design procedure for electrically small reflector antennas. Fabrication and measurement of a prototype antenna support the theory.

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1 MHz to 3 GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.