The c-Secure CRT code is a collusion-secure fingerprinting code whose code length is reduced by using the Chinese Remainder Theorem. The tracing algorithm for the c-secure CRT code drops its performance of traitor tracing when random errors are added to the codewords. In this paper, we show two approaches to enhance random-error-resilience to the tracing algorithm of the c-secure CRT code. The first approach is introducing thresholds for the distinction of the detected part of the embedded data called detected blocks. We propose a method to derive appropriate values of the thresholds on an assumption that the tracer can estimate the random error rate. This modification extends the capability of traitor tracing to the attacks in which the alteration rate of the detected blocks is not fixed to 0.5. The second approach is extending the scope of the search for the detected blocks. With numerical results by computer simulations, we confirmed an impressive improvement of random-error-resilience of a c-secure CRT code.

The main contribution of this paper is to present an FPGA-based implementation of an instance-specific hardware which accelerates the CKY (Cocke-Kasami-Younger) parsing for context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines whether G derives x. We have developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any given context-free grammar G. The generated source is embedded in an FPGA using the design software provided by the FPGA vendor. We evaluated the instance-specific hardware, generated by our hardware generator, using a timing analyzer and tested it using the Altera FPGAs. The generated hardware attains a speed-up factor of approximately 750 over the software CKY parsing algorithm.

Mathematical analysis of the average behavior of the AVL balanced tree insertion algorithm has not ever been done completely. As the first step toward this analysis, we have proposed an approximate analysis based on the assumption that all AVL balanced trees with a given number of nodes and height are constructed with equal probability. In this paper, we propose a new analysis of the AVL balanced tree insertion algorithm in conformity with that all n! permutations of n keys occur with equal probability. First we derive the formulae to enumerate the number of permutations constructing the AVL balanced trees with a given number of nodes and height. Then, we propose the formulae to evaluate the average behavior of the AVL balanced tree insertion algorithm and show some results from the proposed formulae.

A broadband access network is required for supporting the increased Internet data traffic. One of the most cost-effective solutions is the Ethernet Passive Optical Networks (E-PONs) with the efficient bandwidth assignment function by which the upstream bandwidth can be shared among access users. To satisfy the services with heterogeneous QoS characteristics, it is very important to provide QoS guaranteed network access while utilize the bandwidth efficiently. In this paper, a dual DEB-GPS scheduler in E-PON is presented to provide delay-constraint and lossless QoS guarantee to QoS service and maximize the bandwidth to best-effort service. Simulation results show our scheme outperforms the conventional bandwidth allocation scheme in E-PON system.

We report field emission from multilayered cathodes grown on silicon and glass substrates. The cathode consist of a layer of nanoseeded diamond and overlayers of nanocluster carbon (sp2 bonded carbon) and tetrahedral amorphous carbon (predominantly sp3 bonded carbon). These films exhibit good field emission characteristics with an electron emission current density of 1µA/cm2, at a field of 5.1V/µm. The multilayered cathodes on silicon substrates exhibit even lower emission threshold field of about 1-2V/µm for an emission current density of 1µA/cm2. The emission is influenced by the nanoseeded diamond size and concentration and the properties of the nano carbon over layer.

This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array which enables dynamic and autonomous reconfiguration of the logic circuits. The LSI was completed by successfully introducing two specific features: fully asynchronous logic circuits and a homogeneous structure, only LUTs are used.

This paper studies the necessity of local CFAR processing in CFAR detection with multisensors. This necessity is shown by comparison between centralized CFAR detection and the distributed CFAR detection scheme based on local CFAR processing, under three typical backgrounds and in several cases of mismatching ρ, the relative ratio of local clutter power level in sensors in a homogeneous background. Results show that centralized CFAR processing can not be considered as CFAR without exact prior knowledge of ρ. In addition, even if the knowledge of ρ is available, the great difference among local clutter power levels can also result in severe performance degradation of centralized CFAR processing. In contrast, the distributed CFAR detection based on local CFAR processing is not affected by ρ at all, a fact which was proposed in a previous published paper. Therefore, the CFAR processing must be made locally in sensors for CFAR detection with multisensors.

A configurable device "PCA-Chip2" implements the concept of Plastic Cell Architecture, which is an extension of programmable logic devices. This paper presents basic design tools for the PCA-Chip2 as the first step to develop the total design environment. Given a C description of a target function, configuration data for PCA-Chip2 is automatically generated by the tools. Trial designs by the tools are also presented to demonstrate the practicability of the proposed approach.

We have formed simple polarization-controller arrays by inserting liquid crystal (LC) in trenches cut across planar lightwave circuits (PLCs). We fabricated LC layers for use as polarization controllers on PLCs in two ways; in one, the ultra-thin layer of LC is held in a cell that is inserted into a trench on the PLC while in the other, the trench is directly filled with the LC. The ultra-thin LC cell can change the phase of 1.55-µm light from 0 to 3π while the LC filling can change the phase of light at the same wavelength from 0 to 12π below 5Vrms. Two former parallel-aligned ultra-thin LC cells, where the directions of alignment of the liquid crystals are rotated by 45 relative to each other, are capable of converting light with an arbitrary input polarization to TE or TM polarization. Ultra-thin cells of twisted nematic LC can switch the polarization between TE and TM modes with an extinction ratio of -15dB. The array we fabricated had a pitch of 1 mm and 5 elements, but an array with more than 100 elements and a pitch below 125µm will easily be possible by using finely patterned transparent electrodes. We have also applied our techniques to the fabrication of LC-based variable optical attenuators (VOA) on the PLC.

It is found that the supercontinuum spectrum is generated from cross-phase modulated soliton pulses which are propagated through a dispersion-flattened/decreasing fiber with low birefringence. The cross-phase modulation is achieved by exciting two orthogonally polarized modes in a birefringent fiber and the effect of input azimuth of linearly polarized pulses is discussed theoretically and numerically.

Lin and Jan recently proposed a new automatic signature scheme using a compiler in distributed systems. The proposed scheme adopts a digital signature scheme to detect the change of computer programs, thus it allows computer programs prevent from the infection of computer viruses. However, this article will present a forgery signature attack on their scheme. Moreover, the author also points out one restriction in their scheme. It is impractical for most application programs.

The achievable rate region related to the problem of generating mutually independent random sequences is determined. Furthermore, it is proved that the output distribution of lossless source encoders with correlated side information is asymptotically independent of the side information. Based on this, we can realize a random number generator that produces mutually asymptotically independent random sequences from random sequences emitted from correlated sources.

Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.

In this paper, the problem of output feedback passification for nonlinear systems is considered. Contrary to the conventional methodologies, our approach does not require the normal form representation of the system. Consequent advantages include that the system need not have a well-defined relative degree. In particular, we present a necessary and sufficient condition for output feedback passification without relying on the normal form. The proposed condition finally leads to an extension for a recent result when the system does have a normal form.

A new algorithm for efficient arithmetic in an optimal extension field is proposed. The new algorithm improves the speeds of multiplication, squaring, and inversion by performing two subfield multiplications simultaneously within a single integer multiplication instruction of a CPU. Our algorithm is used to improve throughputs of elliptic curve operations.

We designed an FPGA-based parallel machine called "RASH"(Reconfigurable Architecture based on Scalable Hardware) for high speed and flexible signal/data processing. Cryptanalysis is one of the killer applications for FPGA-based machines because huge amounts of logical and/or simple arithmetic operations are required and FPGA is suitable for this. One of the well-known activities in cryptanalysis is the DES (Data Encryption Standard) cracking contest conducted by RSA Data Security. TMTO (Time-Memory Trade-Off) Cryptanalysis is a practical method to dramatically shorten the time for key search when plaintext is given in advance. A string of ASCII characters is used as the key much like a password. The ASCII character is 7-bit character and is changed to 96 kinds of value. The 56-bit DES key is given with a string of 8 ASCII characters. Although the DES key has 64 trillion(=256) possibilities, the key that is given with a string has only 6.4 trillion(=968) possibilities. Therefore, we improve TMTO cryptanalysis so that we search only the limited key by ASCII characters and reduce the quantity of computation. In this paper, we demonstrate how TMTO cryptanalysis for limited key is well suited to our FPGA-based RASH machine. By limiting the key to a string, DES key will be found at 80% probability within 45 minutes after ciphertext is given on 10 units of RASH. The precomputation before starting key search takes 3 weeks on the same RASH configuration.

This paper presents an innovative 155Mb/s burst-mode laser transmitter chip, which was designed and successfully demonstrated, and contains several new subsystems: a digitally programmed current source, programmable up to 120mA with a resolution of 0.1mA, a fast but accurate intermittent optical level monitoring circuit, and a digital Automatic Power Control (APC) algorithm. This generic and intelligent chip was developed in a standard digital 0.35µm CMOS process. Extensive testing showed a high yield and algorithm stability, as well as excellent performance. During initialization, when the transmitter is connected to the Passive Optical Network (PON) for the first time, maximum three Laser Control Fields (LCF) are needed, with a length of 17bytes (0.88microsecond at 155Mb/s), to stabilize the laser output power. In this short time, the chip can regulate the launched optical output power of any FSAN (Full Service Access Network) compliant laser diode to the required level, even in the extreme circumstances caused by outdoor operation or by battery backup operation during power outages. Other tests show that the chip can further stabilize and track this launched optical power with a tolerance lower than 1dB over a wide temperature range, during the burst mode data transmission. The APC algorithm intermittently adjusts the optical power to be transmitted in a digital way, starting from loosely specified but safe preset values, to the required stable logic "1" and "0" level. No laborious calibration of the laser characteristic curve and storage of the calibration values in lookup tables are needed, nor any off-chip adjustable component. The power consumption is significantly reduced by disabling inactive circuitry and by gating the digital high-speed clock. Although this laser transmitter was developed for FSAN PON applications, which are standardized at a speed of 155Mb/s upstream, the design concept is quite generic and can be applied for developing a wide range of burst mode laser transmitters, such as required for Gigabit PON systems or other TDMA networks.

Fingerprinting is one of the digital watermarking techniques, and is becoming more important as a copyright protection technique. Fingerprinting must resist collusion attacks. As a security index, "c-secureness" has been proposed, but it has been known that there is indeed no c-secure code. In this paper, we introduce a new index to measure the resilience of fingerprinting for collusion attacks and obtain some upper bounds and a lower bound on the index.

Piecewise linear (PWL) circuit modules operating on sigma-delta (ΣΔ) modulated signals and nonlinear signal processors built of these modules are proposed. The proposed module library includes absolute circuits, min/max selectors and negative resistances. Their output signal-to-noise ratio is higher than 50dB when their oversampling ratio is 28. A nonlinear filter and a stochastic resonator are presented as applications of the PWL modules to ΣΔ domain signal processing. The filter is structured with 37% of logic gates consumed by an equivalent filter with a 5-bit parallel signal form.

In this paper, the efficient structure of an LUT (look-up table) for an asynchronous reconfigurable PCA (Plastic Cell Architecture) device is investigated. A total of 15 types of implementation alternatives for LUTs are evaluated and compared in an empirical manner in which full custom layout design is developed and simulated. The evaluation results show that by introducing transmission gates in memory cells in an LUT, read time can be improved by 14.3% at the cost of 13.6% area increase compared to a conventional speed oriented implementation. It is also shown that use of transmission gates reduces 6.4% of area and 19.2% of read time against a conventional area oriented LUT implementation.