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[Keyword] SI(16314hit)

11261-11280hit(16314hit)

  • Intra-Channel Nonlinearities and Dispersion-Management in Highly Dispersed Transmission

    Sang-Gyu PARK  Je-Myung JEONG  

     
    PAPER-Fiber-Optic Transmission

      Vol:
    E86-B No:4
      Page(s):
    1205-1211

    This study is a detailed numerical investigation on the relations between the performance of the RZ format single-channel transmission, and the chromatic dispersion of transmission fiber and pre-compensation ratio. We observed the transition from the SPM dominant low dispersion region to the intra-channel nonlinearities dominant high dispersion region, and found that the EOP is very sensitive to the pre-compensation ratio when the dispersion assumes a intermediate value. Furthermore, by analyzing the optical power-dependence of the EOP and other nonlinear impairments, we found that the amplitude fluctuation resulting from IFWM is dominant in determining the EOP in the transmission systems employing highly dispersed pulses.

  • Error Concealment Based on Motion Vector Recovery Using Optical Flow Fields

    Jae-Won SUH  Yo-Sung HO  

     
    PAPER-Multimedia Systems

      Vol:
    E86-B No:4
      Page(s):
    1383-1390

    Compressed video bitstreams are very sensitive to transmission errors. If we lose packets or receive them with errors during transmission, not only the current frame will be corrupted, but also errors will propagate to succeeding frames. Therefore, we need various mechanisms to protect data and reduce the effects of transmission errors. Error concealment is a data recovery technique that enables the decoder to conceal the effects of transmission errors by predicting the lost or corrupted video data from the previously reconstructed error free information. Motion vector recovery and motion compensation with the estimated motion vector is a good approach to conceal the corrupted macroblock data. In this paper, we show that it is reasonable to use the estimated motion vector to conceal the lost macroblock by providing macroblock distortion models. After we propose a new motion vector recovery algorithm based on optical flow fields, we compare its performance to those of conventional error concealment methods.

  • New Algorithms for Working and Spare Capacity Assignment in Integrated Self-Healing Networks

    Michael LOGOTHETIS  Ioannis NIKOLAOU  

     
    PAPER-Network

      Vol:
    E86-B No:4
      Page(s):
    1346-1355

    Modern network technologies gave rise to intelligent network reconfiguration schemes for restoration purposes and several network self-healing schemes, exploiting the capabilities of network elements (NE), have already been proposed. Each self-healing scheme has its own characteristics, regarding restoration time, flexibility, restoration cost and exploitation of NEs. Integrated self-healing networks, which combine more than one survivability techniques, mainly the Shared Self-Healing Rings (SSR) with the Dynamic Self-Healing Networks (DSN), can achieve higher network survivability and cost-effective network design. In this paper, we propose two algorithms for the design of spare and working channel capacities for integrated self-healing networks. In the first algorithm, A1, we do not take into account the capacity of network nodes, while in the second algorithm, A2, we take into account the limited capacity of network nodes. These algorithms are based on the shortest path principles, similarly to a previous algorithm (old algorithm) proposed by scientists of NEC Corporation for integrated self-healing network design. By the new algorithms we achieve more savings than by the old algorithm in total network capacity. On the other hand, strong motivation for the development of the new algorithms is the fact that the procedural steps of the old algorithm are not homogeneous; the old algorithm incorporates both heuristics and analytical methods, in contrast to the new algorithms that are pure heuristics. Moreover, we introduce restrictions in node-capacities of the network that they were not included in the old algorithm.

  • Single Code Cyclic Shift Detection--ddash A Pilot Aided CDMA Multiuser Detector without Using Explicit Knowledge of Signature Codes

    Hsiao-Hwa CHEN  Yi-Ning CHANG  Yu-Bing WU  

     
    PAPER-Terrestrial Radio Communications

      Vol:
    E86-B No:4
      Page(s):
    1286-1296

    A new pilot-aided multiuser detection scheme, single code cyclic shift (SCCS) detector, is proposed in this paper for synchronous CDMA multiuser signal reception. The unique feature of the proposed detector is that a receiver can decode multiuser signals even without explicit knowledge of all signature codes active in the system. The transmitting signal from a base station to a mobile contains two separated channels: the pilot and data channels; the former consists of periodically repeated pilot symbols encoded by the same signature codes as the one spreading the latter. Both pilot and data signals for a specific mobile are sent by a base-station using quadrature and in-phase carriers at the same frequency with QPSK modulation. A matched filter bank, consisting of M correlators that match to distinct cyclic-shifted versions of a "single" signature code, is employed for "channel cyclic shift correlation function" estimation, followed by the multiuser detection algorithm based on the channel information obtained earlier. The performance of the proposed SCCS detector is evaluated and compared to decorrelating detector by computer simulations considering various multipath channels with different profiles. The results demonstrate that a synchronous CDMA joint detection can be implemented successfully without necessarily knowing all signature codes of the system.

  • Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design

    Norio OHKUBO  Takeo YAMASHITA  

     
    PAPER-Design Methods and Implementation

      Vol:
    E86-C No:4
      Page(s):
    618-623

    An accurate, fast delay calculation method suitable for high-performance, low-power LSI design is proposed. The delay calculation is composed of two steps: (1) the gate delay is calculated by using an effective capacitance obtained from a simple model we propose; and (2) the interconnect delay is also calculated from the effective capacitance and modified by using the gate-output transition time. The proposed delay calculation halves the error of a conventional rough calculation, achieving a computational error within 10% per gate stage. The mathematical models are simple enough that the method is suitable for quick delay calculation and logic circuit optimization in the early stages of LSI design. A delay optimization tool using this delay calculation method reduced the worst path delay of a multiply-add module by 11.2% and decreased the sizes of 58.1% of the gates.

  • PAE Improvement of PCS MMIC Power Amplifier with a Bias Control Circuit

    Ji Hoon KIM  Joon Hyung KIM  Youn Sub NOH  Song Gang KIM  Chul Soon PARK  

     
    LETTER-Microwaves, Millimeter-Waves

      Vol:
    E86-C No:4
      Page(s):
    672-675

    A high efficient HBT MMIC power amplifier with a new on-chip bias control circuit was proposed for PCS applications. By adjusting the quiescent current in accordance with the output power levels, the average power usage efficiency of the power amplifier is improved by a factor of 1.4. The bias controlled power amplifier, depending on low (high) output power levels, shows 62(103) mA of quiescent current, 16(28) dBm output power with 7.5(35.4)% of power-added efficiency(PAE), -46(-45) dBc of adjacent-channel power ratio (ACPR), and 23.7(26.9) dB of gain

  • A Low-Power MPEG-4 Codec LSI for Mobile Video Application

    Peilin LIU  Li JIANG  Hiroshi NAKAYAMA  Toshiyuki YOSHITAKE  Hiroshi KOMAZAKI  Yasuhiro WATANABE  Hisakatsu ARAKI  Kiyonori MORIOKA  Shinhaeng LEE  Hajime KUBOSAWA  Yukio OTOBE  

     
    PAPER-Design Methods and Implementation

      Vol:
    E86-C No:4
      Page(s):
    652-660

    We have developed a low-power, high-performance MPEG-4 codec LSI for mobile video applications. This codec LSI is capable of up to CIF 30-fps encoding, making it suitable for various visual applications. The measured power consumption of the codec core was 9 mW for QCIF 15-fps codec operation and 38 mW for CIF 30-fps encoding. To provide an error-robust MPEG-4 codec, we implemented an error-resilience function in the LSI. We describe the techniques that have enabled low power consumption and high performance and discuss our test results.

  • A Sub-1 V Bootstrap Pass-Transistor Logic

    Koji FUJII  Takakuni DOUSEKI  

     
    PAPER-Circuit Design

      Vol:
    E86-C No:4
      Page(s):
    604-611

    A pass-transistor logic is enhanced with a bootstrap configuration for sub-1 V operation at high speed and low power. The bootstrap configuration drives the output to full swing, which accelerates the signal transition and cuts off the short-circuit current of subsequent CMOS logic gates. The asynchronous or synchronous timing sequence of the input (drain) and the control (gate) signals ensures bootstrap operation. A 1-b arithmetic logic unit (ALU) and an EXNOR gate built with the bootstrap pass-transistor logic outperforms those built with other types of pass-transistor logic. An experimental 16-b pass-transistor adder operates down to 0.4 V with a delay time of 4.2 ns and a power dissipation of 2.8 µ W/MHz at 0.5 V.

  • An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video

    Masayuki MIYAMA  Osamu TOOYAMA  Naoki TAKAMATSU  Tsuyoshi KODAKE  Kazuo NAKAMURA  Ai KATO  Junichi MIYAKOSHI  Kousuke IMAMURA  Hideo HASHIMOTO  Satoshi KOMATSU  Mikio YAGI  Masao MORIMOTO  Kazuo TAKI  Masahiko YOSHIMOTO  

     
    PAPER-Architecture and Algorithms

      Vol:
    E86-C No:4
      Page(s):
    561-569

    This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a Gradient Descent Search (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SIMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50 mm 3.35 mm area using 0.13 µm CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.

  • Blind Image Identification and Restoration for Noisy Blurred Images Based on Discrete Sine Transform

    Dongliang HUANG  Naoyuki FUJIYAMA  Sueo SUGIMOTO  

     
    PAPER-Image Processing, Image Pattern Recognition

      Vol:
    E86-D No:4
      Page(s):
    727-735

    This paper presents a maximum likelihood (ML) identification and restoration method for noisy blurred images. The unitary discrete sine transform (DST) is employed to decouple the large order spatial state-space representation of the noisy blurred image into a bank of one-dimensional real state-space scalar subsystems. By assuming that the noises are Gaussian distributed processes, the maximum likelihood estimation technique using the expectation-maximization (EM) algorithm is developed to jointly identify the blurring functions, the image model parameters and the noise variances. In order to improve the computational efficiency, the conventional Kalman smoother is incorporated to give the estimates. The identification process also yields the estimates of transformed image data, from which the original image is restored by the inverse DST. The experimental results show the effectiveness of the proposed method and its superiority over the recently proposed spatial domain DFT-based methods.

  • Image Compression with Wavelet-Based Vector Quantization

    Shinfeng D. LIN  Shih-Chieh SHIE  Kuo-Yuan LEE  

     
    LETTER-Image Processing, Image Pattern Recognition

      Vol:
    E86-D No:4
      Page(s):
    763-767

    A wavelet-based vector quantization scheme for image compression is introduced here. The proposed scheme obtains a better compression efficiency by the following three methods. (1) Utilizing the correlation among wavelet coefficients. (2) Placing different emphasis on wavelet coefficients at different levels. (3) Preserving the most important information of the image. In our experiments, simulation results show that this technique outperforms the recent SMVQ-ABC [1] and WTC-NIVQ [2] techniques.

  • A Dynamic Node Decaying Method for Pruning Artificial Neural Networks

    Md. SHAHJAHAN  Kazuyuki MURASE  

     
    PAPER-Biocybernetics, Neurocomputing

      Vol:
    E86-D No:4
      Page(s):
    736-751

    This paper presents a dynamic node decaying method (DNDM) for layered artificial neural networks that is suitable for classification problems. Our purpose is not to minimize the total output error but to obtain high generalization ability with minimal structure. Users of the conventional back propagation (BP) learning algorithm can convert their program to the DNDM by simply inserting a few lines. This method is an extension of a previously proposed method to more general classification problems, and its validity is tested with recent standard benchmark problems. In addition, we analyzed the training process and the effects of various parameters. In the method, nodes in a layer compete for survival in an automatic process that uses a criterion. Relatively less important nodes are decayed gradually during BP learning while more important ones play larger roles until the best performance under given conditions is achieved. The criterion evaluates each node by its total influence on progress toward the upper layer, and it is used as the index for dynamic competitive decaying. Two additional criteria are used: Generalization Loss to measure over-fitting and Learning Progress to stop training. Determination of these criteria requires a few human interventions. We have applied this algorithm to several standard benchmark problems such as cancer, diabetes, heart disease, glass, and iris problems. The results show the effectiveness of the method. The classification error and size of the generated networks are comparable to those obtained by other methods that generally require larger modification, or complete rewriting, of the program from the conventional BP algorithm.

  • Diversity Transform of N-DPSK with Decision-Feedback Differential Detection over Correlated Rayleigh Fading

    Fuh-Hsin HWANG  

     
    LETTER-Wireless Communication Technology

      Vol:
    E86-B No:4
      Page(s):
    1457-1461

    In this letter, we investigate a diversity scheme which employs a simple transform, symbol interleaving and decision-feedback differential detection (DF-DD) for differential phase-shift-keying signal transmission over correlated Rayleigh fading. The proposed scheme merits instinct time diversity within each transmitted block and thus presents patent resistance to fading. It is shown that the considered technique provides significant diversity gains in a correlated Rayleigh fading channel.

  • Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits

    Nattha SRETASEREEKUL  Takashi NANYA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E86-A No:4
      Page(s):
    900-907

    The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochronic forks assumed for existing QDI circuits do not actually have to be "isochronic" or can be even ignored.

  • GAHA and GAPA: Two Link-Level Approaches for Supporting Link Asymmetry in Mobile Ad Hoc Networks

    Dongkyun KIM  Chai-Keong TOH  Yanghee CHOI  

     
    PAPER-Terrestrial Radio Communications

      Vol:
    E86-B No:4
      Page(s):
    1297-1306

    Existing routing protocols for mobile ad hoc networks assume that all nodes have the same transmission range. In other words, the mobile ad hoc network has symmetric links, which means that two neighboring nodes A and B are within the transmission range of one another. However, since nodes consume battery power independently according to their computing and communication load, there exist asymmetric links, which means that node A is within node B's transmission range, but not vice versa. In this paper, two approaches are presented to support routing in the existence of asymmetric links: GAHA (GPS-based Hop-by-hop Acknowledgment) and GAPA (GPS-based Passive Acknowledgment) schemes. Both GAHA and GAPA can be applied to any routing protocols by utilizing GPS (Global Positioning System) location information. Simulation results reveal that both GAHA and GAPA protocols cope well in the presence of asymmetric wireless links and nodes' mobility.

  • Dynamic Channel Assignment and Reassignment for Exploiting Channel Reuse Opportunities in Ad Hoc Wireless Networks

    Chih-Yung CHANG  Po-Chih HUANG  Chao-Tsun CHANG  Yuh-Shyan CHEN  

     
    PAPER-Wireless Communication Technology

      Vol:
    E86-B No:4
      Page(s):
    1234-1246

    In Ad Hoc networks, communication between a pair of hosts uses channel resources, such that the channel cannot be used by the neighboring hosts. A channel used by one pair of hosts can be reused by another pair of hosts only if their communication ranges do not overlap. Channels are limited resources, accounting for why exploiting channel reuse opportunities and enhancing the channel utilization is essential to increasing system capacity. However, exploiting channel reuse opportunities may cause a co-channel interference problem. Two pairs of communicating hosts that use the same channel may gradually move toward to each other. A channel reassignment operation must be applied to these hosts to maintain their communication. This investigation presents a channel assignment protocol that enables the channel resources to be highly utilized. Following this protocol, a channel reassignment protocol is also proposed to protect the communicating hosts from co-channel interference caused by mobility. The proposed reassignment protocol efficiently reassigns a new available channel to a pair of hosts that suffers from co-channel interference. The performance of the proposed protocols is also examined. Experimental results reveal that the proposed protocols enable more hosts to communicate simultaneously and prevent their communication from failing.

  • Load Fluctuation-Based Dynamic File Allocation with Cost-Effective Mirror Function

    Jun TAKAHASHI  Akiko NAKANIWA  Yasutomo ABE  Hiroyuki EBARA  Hiromi OKADA  

     
    PAPER-Network

      Vol:
    E86-B No:4
      Page(s):
    1317-1326

    Mirroring of network servers has been considered to be effective for load balancing. However, the cost of setting up new mirror servers is enormously high. In this paper, we propose a dynamic file allocation model with a simple mirroring function for handling significant changes of network traffic in the Internet. According to the load fluctuation, we can dynamically reallocate files using this model. We show that our model accomplishes satisfactory performance and reduces cost by adding a simple mirroring function to all existent servers instead of setting up mirror servers afresh.

  • An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter

    Seung-Chan HEO  Young-Chan JANG  Sang-Hune PARK  Hong-June PARK  

     
    LETTER-Electronic Circuits

      Vol:
    E86-C No:4
      Page(s):
    676-681

    An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

  • Blind Source Separation of Acoustic Signals Based on Multistage ICA Combining Frequency-Domain ICA and Time-Domain ICA

    Tsuyoki NISHIKAWA  Hiroshi SARUWATARI  Kiyohiro SHIKANO  

     
    PAPER-Digital Signal Processing

      Vol:
    E86-A No:4
      Page(s):
    846-858

    We propose a new algorithm for blind source separation (BSS), in which frequency-domain independent component analysis (FDICA) and time-domain ICA (TDICA) are combined to achieve a superior source-separation performance under reverberant conditions. Generally speaking, conventional TDICA fails to separate source signals under heavily reverberant conditions because of the low convergence in the iterative learning of the inverse of the mixing system. On the other hand, the separation performance of conventional FDICA also degrades significantly because the independence assumption of narrow-band signals collapses when the number of subbands increases. In the proposed method, the separated signals of FDICA are regarded as the input signals for TDICA, and we can remove the residual crosstalk components of FDICA by using TDICA. The experimental results obtained under the reverberant condition reveal that the separation performance of the proposed method is superior to those of TDICA- and FDICA-based BSS methods.

  • Further Cryptanalysis of a Password Authentication Scheme with Smart Cards

    Hung-Min SUN  Her-Tyan YEH  

     
    LETTER-Fundamental Theories

      Vol:
    E86-B No:4
      Page(s):
    1412-1415

    Following the developments in the use of ID-based schemes and smart cards, Yang and Shieh proposed two password authentication schemes to achieve two purposes: (1) to allow users to choose and change their passwords freely, and (2) to make it unnecessary for the remote server to maintain a directory of passwords or a verification table to authenticate users. Recently, Chan and Cheng showed that Yang and Shieh's timestamp-based password authentication scheme is insecure against forgery. In this paper, we point out that Chan and Cheng's forgery attack can not work. Thus, we further examine the security of Yang and Shieh's password authentication schemes and find that they are insecure against forgery because one adversary can easily pretend to be a valid user and pass the server's verification which allows the adversary to login to the the remote server.

11261-11280hit(16314hit)