We have developed a low-power, high-performance MPEG-4 codec LSI for mobile video applications. This codec LSI is capable of up to CIF 30-fps encoding, making it suitable for various visual applications. The measured power consumption of the codec core was 9 mW for QCIF 15-fps codec operation and 38 mW for CIF 30-fps encoding. To provide an error-robust MPEG-4 codec, we implemented an error-resilience function in the LSI. We describe the techniques that have enabled low power consumption and high performance and discuss our test results.

A high efficient HBT MMIC power amplifier with a new on-chip bias control circuit was proposed for PCS applications. By adjusting the quiescent current in accordance with the output power levels, the average power usage efficiency of the power amplifier is improved by a factor of 1.4. The bias controlled power amplifier, depending on low (high) output power levels, shows 62(103) mA of quiescent current, 16(28) dBm output power with 7.5(35.4)% of power-added efficiency(PAE), -46(-45) dBc of adjacent-channel power ratio (ACPR), and 23.7(26.9) dB of gain

An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

A wavelet-based vector quantization scheme for image compression is introduced here. The proposed scheme obtains a better compression efficiency by the following three methods. (1) Utilizing the correlation among wavelet coefficients. (2) Placing different emphasis on wavelet coefficients at different levels. (3) Preserving the most important information of the image. In our experiments, simulation results show that this technique outperforms the recent SMVQ-ABC [1] and WTC-NIVQ [2] techniques.

This paper presents a dynamic node decaying method (DNDM) for layered artificial neural networks that is suitable for classification problems. Our purpose is not to minimize the total output error but to obtain high generalization ability with minimal structure. Users of the conventional back propagation (BP) learning algorithm can convert their program to the DNDM by simply inserting a few lines. This method is an extension of a previously proposed method to more general classification problems, and its validity is tested with recent standard benchmark problems. In addition, we analyzed the training process and the effects of various parameters. In the method, nodes in a layer compete for survival in an automatic process that uses a criterion. Relatively less important nodes are decayed gradually during BP learning while more important ones play larger roles until the best performance under given conditions is achieved. The criterion evaluates each node by its total influence on progress toward the upper layer, and it is used as the index for dynamic competitive decaying. Two additional criteria are used: Generalization Loss to measure over-fitting and Learning Progress to stop training. Determination of these criteria requires a few human interventions. We have applied this algorithm to several standard benchmark problems such as cancer, diabetes, heart disease, glass, and iris problems. The results show the effectiveness of the method. The classification error and size of the generated networks are comparable to those obtained by other methods that generally require larger modification, or complete rewriting, of the program from the conventional BP algorithm.

This paper presents a maximum likelihood (ML) identification and restoration method for noisy blurred images. The unitary discrete sine transform (DST) is employed to decouple the large order spatial state-space representation of the noisy blurred image into a bank of one-dimensional real state-space scalar subsystems. By assuming that the noises are Gaussian distributed processes, the maximum likelihood estimation technique using the expectation-maximization (EM) algorithm is developed to jointly identify the blurring functions, the image model parameters and the noise variances. In order to improve the computational efficiency, the conventional Kalman smoother is incorporated to give the estimates. The identification process also yields the estimates of transformed image data, from which the original image is restored by the inverse DST. The experimental results show the effectiveness of the proposed method and its superiority over the recently proposed spatial domain DFT-based methods.

A fast-motion-estimation (ME) algorithm called a "breaking-off-search (BOS)" was developed. It can improve processing speed of the full-search (FS) method by a factor of 3.4. The BOS algorithm can not only sometimes achieve better visual quality than FS, but can also solve visual degradation problems associated with conventional fast-ME algorithms whenever picture patterns change (i. e. , presence of scene changes). The power dissipation of a 0.6-µ m CMOS parallel Wallace-tree motion estimator using BOS was reduced to about 281 mW which was 1/28.7 that of the 0.6-µ m CMOS binary-tree motion estimator using FS.

This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a Gradient Descent Search (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SIMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50 mm 3.35 mm area using 0.13 µm CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.

A pass-transistor logic is enhanced with a bootstrap configuration for sub-1 V operation at high speed and low power. The bootstrap configuration drives the output to full swing, which accelerates the signal transition and cuts off the short-circuit current of subsequent CMOS logic gates. The asynchronous or synchronous timing sequence of the input (drain) and the control (gate) signals ensures bootstrap operation. A 1-b arithmetic logic unit (ALU) and an EXNOR gate built with the bootstrap pass-transistor logic outperforms those built with other types of pass-transistor logic. An experimental 16-b pass-transistor adder operates down to 0.4 V with a delay time of 4.2 ns and a power dissipation of 2.8 µ W/MHz at 0.5 V.

In this letter, we investigate a diversity scheme which employs a simple transform, symbol interleaving and decision-feedback differential detection (DF-DD) for differential phase-shift-keying signal transmission over correlated Rayleigh fading. The proposed scheme merits instinct time diversity within each transmitted block and thus presents patent resistance to fading. It is shown that the considered technique provides significant diversity gains in a correlated Rayleigh fading channel.

When decision-directed channel estimation is used for QAM-OFDM systems, the optimal filter shape depends on the amplitudes of the modulated symbols as well as the channel characteristics. In this letter we propose a simple channel estimation method for multi-level-amplitude-modulated systems, which can effectively suppress the estimation variances with a small filter. Using the proposed method the implementation cost can be reduced and possibly better results might be obtained by avoiding the estimation bias due to large-sized filtering.

This paper investigates a new method for creating robust speaker models to cope with inter-session variation of a speaker in a continuous HMM-based speaker verification system. The new method estimates session-independent parameters by decomposing inter-session variations into two distinct parts: session-dependent and -independent. The parameters of the speaker models are estimated using the speaker adaptive training algorithm in conjunction with the equalization of session-dependent variation. The resultant models capture the session-independent speaker characteristics more reliably than the conventional models and their discriminative power improves accordingly. Moreover we have made our models more invariant to handset variations in a public switched telephone network (PSTN) by focusing on session-dependent variation and handset-dependent distortion separately. Text-independent speech data recorded by 20 speakers in seven sessions over 16 months was used to evaluate the new approach. The proposed method reduces the error rate by 15% relatively. When compared with the popular cepstral mean normalization, the error rate is reduced by 24% relatively when the speaker models were recreated using speech data recorded in four or more sessions.

A novel postprocessing algorithm for reducing the blocking artifacts in block-based coded images is proposed using block classification and adaptive multi-layer perceptron (MLP). This algorithm is exploited the nonlinearity property of the neural network learning algorithm to reduce the blocking artifacts more accurately. In this algorithm, each block is classified into four classes; smooth, horizontal edge, vertical edge, and complex blocks, based on the characteristic of their discrete cosine transform (DCT) coefficients. Thereafter, according to the class information of the neighborhood block, adaptive neural network filters (NNF) are then applied to the horizontal and vertical block boundaries. That is, for each class a different two-layer NNF is used to remove the blocking artifacts. Experimental results show that the proposed algorithm produced better results than conventional algorithms both subjectively and objectively.

In this letter, we propose a new technique that reduces the computation time to derive the MEI coefficients in solving scattering problems by the Measured Equation of Invariance (MEI) methods. Methods that use the MEI technique spend most of the computation time in the integration process to derive the MEI coefficients. Moreover, in the conventional solution process, some repeated computation of metron fields to derive the MEI coefficients is included. To avoid the repeated operations and thus save computation time, we propose a matrix localization technique in computing the MEI coefficients. The time comparison for the computation of MEI coefficients of a cylinder and a sphere is given to verify the CPU time reduction of our new technique.

This paper describes multigrain parallel processing on OSCAR (Optimally SCheduled Advanced multiprocessoR) chip multiprocessor architecture. OSCAR compiler cooperative chip multiprocessor architecture aims at development of scalable, high effective performance and cost effective chip multiprocessor with ease of use by compiler supports. OSCAR chip multiprocessor architecture integrates simple single issue processors having distributed shared data memory for optimal use of data locality over different loops and fine grain data transfer and synchronization, local data memory for private data recognized by compiler, and compiler controllable data transfer unit for overlapping data transfer to hide data transfer overhead. This OSCAR chip multiprocessor and OSCAR multigrain parallelizing compiler have been developed simultaneously. Performance of multigrain parallel processing on OSCAR chip multiprocessor architecture is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR chip multiprocessor architecture gives us 2.36 times speedup in fpppp, 2.64 times in su2cor, 2.88 times in turb3d, 2.98 times in hydro2d, 3.84 times in tomcatv, 3.84 times in mgrid and 3.97 times in swim respectively for four processors against single processor.

In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (ION), SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.

In this letter, base station placement is automatically determined from pre-defined candidate sites using a genetic approach, and the transmit power is obtained taking the interference situation into account in cases of interference-dominant systems. In order to apply a genetic algorithm to the base station placement problem, a real-valued representation scheme is proposed. Corresponding operators such as crossover and mutation are also introduced. The proposed algorithm is applied to an inhomogeneous traffic density environment, where a base station's coverage may be limited by offered traffic loads. An objective function is designed for performing the cell planning in a coverage- and cost-effective manner.

A new analysis method for random dopant induced threshold voltage fluctuations by using Monte Carlo ion implantation were presented. The method was applied to investigate Vt fluctuations due to statistical variation of pocket dopant profile in 0.1µm MOSFET's by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFET's efficiently.

Accurate estimation of accentual attribute values of words, which is required to apply rules of Japanese word accent sandhi to prosody generation, is an important factor to realize high-quality text-to-speech (TTS) conversion. The rules were already formulated by Sagisaka et al. and are widely used in Japanese TTS conversion systems. Application of these rules, however, requires values of a few accentual attributes of each constituent word of input text. The attribute values cannot be found in any public database or any accent dictionaries of Japanese. Further, these values are difficult even for native speakers of Japanese to estimate only with their introspective consideration of properties of their mother tongue. In this paper, an algorithm was proposed, where these values were automatically estimated from a large amount of data of accent types of accentual phrases, which were collected through a long series of listening experiments. In the proposed algorithm, inter-speaker differences of knowledge of accent sandhi were well considered. To improve the coverage of the estimated values over the obtained data, the rules were tentatively modified. Evaluation experiments using two-mora accentual phrases showed the high validity of the estimated values and the modified rules and also some defects caused by varieties of linguistic expressions of Japanese.

The implant-anneal cycle for B doping during Si device fabrication causes transient enhanced diffusion (TED) of B and the formation of small immobile B-interstitial clusters (BICs) which deactivate the B. Additionally, since modern ultrashallow devices put most of the B in immediate proximity of the Si/SiO2 interface, interface-dopant interactions like segregation become increasingly important. In this work, we use density-functional theory calculations to study TED, clustering, and segregation of B during annealing and discuss a continuum model which combines the TED and clustering results.