A soft-decision decoding scheme of low-density parity-check codes (LDPC) is proposed for hard-detected signals of optical fiber communication (OFC) systems. Based on the error detection, the proposed scheme converts the received hard-decision into soft reliability for the input of the LDPC decoder, and soft-decision decoding is performed. Simulation results under OFC channels are shown and superior performance is obtained by using the proposed decoding scheme of the LDPC codes.

Recently, Stadler et al. proposed the concept of fair blind signatures to prevent the misuse of blind signature schemes from criminals. In this article, we show the proposed scheme could not meet the untraceability property of blind signature's requirements. We point out that the proposed scheme cannot provide true blind signatures.

A simple address indexing method is proposed for path memory management in multi-PE Viterbi decoder, which solves data read/write conflict problem completely. This method not only simplifies control and addressing overhead but also has the advantage of requiring only two memory banks regardless of the number of PE's, with 100% PE utilization.

As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.

To increase the discriminating ability of the speech feature based on linear predictive coding (LPC) and increase its noise robustness, an SNR-dependent arcsin transform is applied to the autocorrelation sequence (ACS) of each analysis frame in a speech signal. Moreover, each component in the ACS is also weighted by the normalized reciprocal of the average magnitude difference function (AMDF) for emphasizing its peak structure. Experimental results for the task of Mandarin digit recognition indicate that the LPC speech feature employing the proposed scheme is more robust than some widely used LPC-based approaches over a wide range of SNR values.

As pseudorandom number generators for Monte Carlo simulations, inversive linear congruential generators (ICG) have some advantages compared with traditional linear congruential generators. It has been shown that a sequence generated by an ICG has a low discrepancy even if the length of the sequence is far shorter than its period. In this paper, we formulate fractional linear congruential generators (FCG), a generalized concept of the inversive linear congruential generators. It is shown that the sequence generated by an FCG is a geometrical shift of a sequence from an ICG and satisfies the same upper bounds of discrepancy. As an application of the general formulation, we show that under certain condition, "Leap-Frog technique," a way of splitting a random number sequence to parallel sequences, can be applied to the ICG or FCG with no extra cost on discrepancy.

The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.

An automated synthesis for analog computational circuits in transistor-level configuration is presented. A cell-based structure is introduced to place moderate constraints on the MOSFET circuit topology. Even though each cell has a simple structure that consists of one current path with four transistors, common analog building blocks can be implemented using combinations of the cells. A genetic algorithm is applied to search circuit topologies and transistor sizes that satisfy given specifications. Synthesis capabilities are demonstrated through examples of three types of computational circuits; absolute value, squaring, and cubing functions by using computer simulations and real hardware.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.

Existing research related to RSVP with mobility support has mainly focused on maintaining reservation state along the routing path, which changes continuously with the movements of mobile host (MH), without much overhead and delay. However, problems such as deepening RSVP's inherent scalability problem and requiring significant changes in the existing network infrastructure have not been adequately addressed. In this paper, we propose a new approach, known as Concatenation and Optimization for Reservation Path (CORP), which addresses these issues. In CORP, each BS pre-establishes pseudo reservations to its neighboring BSs in anticipation of the MH's movement. When the MH moves into another wireless cell, the associated pseudo reservation is activated and concatenated to the existing RSVP session to guarantee continuous QoS support. Because a pseudo reservation is recognized as a normal RSVP session by intermediate routers, little change is required in the current Internet environment to support both movements within a single routing domain and between two different routing domains. CORP also dynamically optimizes the extended reservation path to avoid the infinite path extension problem. Multicast addressing is used to further reduce resource consumption in the optimization process. The experimental results of the CORP implementation demonstrate that it significantly reduces the delay and overhead caused by handoffs compared to the case of establishing a new RSVP session. The improvement increases as the distance between the MH and its correspondent host (CH) grows.

We propose two simple algorithms based on bounded tickets for the mutual exclusion problem on the asynchronous single-writer/multi-reader shared memory model. These algorithms are modifications of the Bakery algorithm. An unattractive property of the Bakery algorithm is that the size of its shared memory is unbounded. Initially we design a provisional algorithm based on bounded tickets. It guarantees mutual exclusion in the case where a certain condition is satisfied. To remove the condition, we use an additional process that does not correspond to any user. The algorithm with the additional process is a lockout-free mutual exclusion algorithm on the asynchronous single-writer/multi-reader shared memory model. We then modify this algorithm to reduce the shared memory size with the cost of using another additional process. The maximum waiting time using each of the algorithms proposed in this paper is bounded by (n-1)c+O(nl), where n is the number of users, l is an upper bound on the time between two successive atomic steps, and c is an upper bound on the time that any user spends using the resource. The shared memory size needed by the first algorithm and the second algorithm are (n+1)(1+log (4n)) bits and n(1+log (4n-4))+2 bits, respectively.

In this paper, we consider the problem of multicasting a message in k-ary n-cubes under the store-and-forward model. The objective of the problem is to minimize the size of the resultant multicast tree by keeping the distance to each destination over the tree the same as the distance in the original graph. In the following, we first propose an algorithm that grows a multicast tree in a greedy manner, in the sense that for each intermediate vertex of the tree, the outgoing edges of the vertex are selected in a non-increasing order of the number of destinations that can use the edge in a shortest path to the destination. We then evaluate the goodness of the algorithm in terms of the worst case ratio of the size of the generated tree to the size of an optimal tree. It is proved that for any k 5 and n 6, the performnance ratio of the greedy algorithm is c kn - o(n) for some constant 1/12 c 1/2.

In this paper, we consider two types of promises for (k-)CNF formulas which can help to find a satisfying assignment of a given formula. The first promise is the Hamming distance between truth assignments. Namely, we know in advance that a k-CNF formula with n variables, if satisfiable, has a satisfying assignment with at most pn variables set to 1. Then we ask whether or not the formula is satisfiable. It is shown that for k 3 and (i) when p=nc (-1 < c 0), the problem is NP-hard; and (ii) when p=log n/n, there exists a polynomial-time deterministic algorithm. The algorithm is based on the exponential-time algorithm recently presented by Schoning. It is also applied for coloring k-uniform hypergraphs. The other promise is the number of satisfying assignments. For a CNF formula having 2n/2nε (0 ε < 1) satisfying assignments, we present a subexponential-time deterministic algorithm based on the inclusion-exclusion formula.

This paper investigates properties of space-bounded "two-dimensional Turing machines (2-tm's)," whose input tapes are restricted to square ones, with bounded input head reversals in vertical direction. We first investigate a relationship between determinism and nondeterminism for space-bounded and input head reversal-bounded 2-tm's. We then investigate how the number of input head reversals affects the accepting power of sublinearly space-bounded 2-tm's. Finally, we investigate necessary and sufficient spaces for three-way 2-tm's to simulate four-way two-dimensional finite automata with constant input head reversals.

This paper describes two digital correction algorithms for ADC nonlinearity, targeted for mixed-signal LSI tester applications: an interpolation algorithm and a stochastic algorithm. Numerical simulations show that our algorithms compensate for ADC nonlinearity as well as missing codes and nonmonotonicity characteristics, and improve ADC SNDR and SFDR.

Unicasting video streams over TCP connections is a challenging problem, because video sources cannot normally adapt to delay and throughput variations of TCP connections. This paper describes a method of extending TCP so that TCP connections can effectively carry hierarchically-encoded layered video streams, while being friendly to other competing connections. We call the method Receiver-based Delay Control (RDC). Under RDC, a TCP connection can slow down its transmission rate to avoid congestion by delaying ACK packet generation at the TCP receiver based on congestion notifications from routers. We present the principle behind RDC, argue that it is TCP-friendly, describe an implementation that uses 1-bit congestion notification from routers, and demonstrate by simulations its effectiveness in streaming hierarchically-encoded layered video.

In the Internet, flow analysis and network monitoring have been studied by various methods. Some methods try to make TCP (Transport Control Protocol) traces more readable by showing them graphically. Others such as MRTG, NetScope, and NetFlow read the traffic counters of the routers and record the data for traffic engineering. Even if all of the above methods are useful, they are made only to perform a single task. This paper describes an improved TCP Protocol Machine, a multipurpose tool that can be used for flow analysis, intrusion detection and link congestion monitoring. It is developed based on a finite state machine (automaton). The machine separates the flows into two main groups. If a flow can be mapped to a set of input symbols of the automaton, it is valid, otherwise it is invalid. It can be observed that intruders' attacks are easily detected by the use of the protocol machine. Also link congestion can be monitored, by measuring the percentage of valid flows to the total number of flows. We demonstrate the capability of this tool through measurement and working examples.

In this paper, a new narrowband beamformer with derivative constraint is developed for wideband and coherent jammers suppression. The so-called IQML algorithm with linear constraint, which is used to estimate the unknown directions of the jammers in signal-free environment, is shown to be an inappropriate constraint estimator. In this paper, a new IQML algorithm with a norm constraint is considered, which is a consistent estimator and can be used to achieve desired performance. It can be also employed in the CDMA system for MAI suppression. We show that it outperforms the approach with the linear constraint used in the narrowband beamformer, in terms of directional pattern, output SINR and nulling capability for wideband and coherent jammers suppression.

We propose herein a motion detection artificial vision model which uses analog electronic circuits. The proposed model is comprised of four layers. The first layer is a differentiation circuit of the large CR coefficient, and the second layer is a differentiation circuit of the small CR coefficient. Thus, the speed of the movement object is detected. The third layer is a difference circuit for detecting the movement direction, and the fourth layer is a multiple circuit for detecting pure motion output. When the object moves from left to right the model outputs a positive signal, and when the object moves from right to left the model outputs a negative signal. We first designed a one-dimensional model, which we later enhanced to obtain a two-dimensional model. The model was shown to be capable of detecting a movement object in the image. Using analog electronic circuits, the number of connections decrease and real-time processing becomes feasible. In addition, the proposed model offers excellent fault tolerance. Moreover, the proposed model can be used to detect two or more objects, which is advantageous for detection in an environment in which several objects are moving in multiple directions simultaneously. Thus, the proposed model allows practical, cheap movement sensors to be realized for applications such as the measurement of road traffic volume or counting the number of pedestrians in an area. From a technological viewpoint, the proposed model facilitates clarification of the mechanism of the biomedical vision system, which should enable design and simulation by an analog electric circuit for detecting the movement and speed of objects.

An efficient algorithm is proposed for finding all solutions of piecewise-linear resistive circuits containing bipolar transistors. This algorithm is based on a powerful test (termed the LP test) for nonexistence of a solution in a given region using linear programming (LP). In the LP test, an LP problem is formulated by surrounding the exponential functions in the Ebers-Moll model by right-angled triangles, and it is solved by LP, for example, by the simplex method. In this paper, it is shown that the LP test can be performed by the dual simplex method, which makes the number of pivotings much smaller. Effectiveness of the proposed technique is confirmed by numerical examples.