This paper describes an effective model which reproduces the dependence on the source/drain (S/D) process of the reverse short channel effect (RSCE) of the MOSFET threshold voltage (Vth). It is useful for local modeling which is effective within the limited process conditions. The proposed model is based on the physics where the key factor of RSCE is the dopant pile-up in the Si/SiO2 interface. The purpose of the model is for TCAD to be put to actual use as a quick solution tool. The calculation cost is much lower than a pair diffusion model, because the model is implemented in a conventional process simulator that solves one equation for each impurity. The capability of the simplified model is investigated for the dependence of various process conditions on the RSCE. Using our model, we also report the application of both the actual n-channel and p-channel MOSFETs.

This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.

In narrow band power-line communication (PLC) systems, which use frequency band below a few hundred kHz, the noise on power-line is non-white and non-stationary. Under such environment, the performance of Orthogonal Frequency Division Multiplex (OFDM) modulation system is analyzed, and time and frequency dependence of bit error rate (BER) is clarified. In addition, the possibility of performance improvement with the symbol level repetition coding employing cyclo-stationary feature of power-line noise is presented.

We investigate dispersion compensation using dispersion-compensating fibers (DCFs) for ultrashort light pulse code division multiple access (CDMA) communication systems in a multi-user environment. We employ fiber link that consists of a standard single-mode fiber (SMF) connected with two different types of DCFs. Fiber dispersion can be effectively decreased by adjusting the length ratios of DCFs to SMF appropriately. Some criteria for dispersion compensation are proposed and their performances are compared. We theoretically derive a bit error rate (BER) of ultrashort light pulse CDMA systems including the effects of the dispersion and multiple access interference (MAI). Moreover, we reveal the mutual relations among BER performance, fiber dispersion, MAI, the number of chips, a bandwidth of a signal, and a transmission distance for the first time. As a result, we show that our compensation strategy improves system performance drastically.

This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.

A blind equalizer which uses the differential constant modulus algorithm (DCMA) is introduced. An anchored FIR equalizer applied to a first-order autoregressive channel and updated according to the DCMA is shown to converge to the inverse of that channel regardless of the initial tap-weights and the gain along the direct path.

The problem of the super-resolution time delay estimation of the real stationary signals is addressed in this paper. The time delay estimation is first converted into a frequency estimation problem. Then a MUSIC-type algorithm to estimate the subsequent frequency from the single-experiment data is proposed, which not only avoids the mathematical model mismatching but also utilizes the advantages of the subspace-based methods. The mean square errors (MSEs) of the time delay estimate of the MUSIC-type method for varying signal-to-noise (SNR) and separation of two received signal components are shown to illustrate that they approximately coincide with the corresponding Cramer-Rao bound (CRB). Finally, the comparison between the MUSIC-type method and the other conventional methods is presented to show the advantages of the proposed method in this paper.

A new approach to build up a real-time multiprocessing system that is configuration flexible for evaluating space-time (ST) equalizers is described. The core of the system consists of fully programmable devices such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and reduced instruction set computers (RISCs) with a real-time operating system (RTOS). The RTOS facilitates flexibility in the multi-processor configuration for the system conforming with ST processing algorithms. Timing jitter synchronization caused by use of the RTOS-embedded system is shown, and an adjustable frame format for a transmission system is described as a measure to avoid the jitter problem. Bit error rate (BER) performances measured in uncorrelated frequency-selective fading channels show that an ST equalizer provides a significantly lower BER than an array processor does.

In this paper, we propose and describe a new synchronizer for the FFT timing applicable to multi-carrier spread-spectrum (MC-SS) communication systems. The performance of the synchronizer is evaluated in terms of false- and miss-detection probabilities in the presence of additive white Gaussian noise (AWGN) and Rayleigh fading.

This paper considers a reconfiguration problem on a processor array model based on single-and-half-track switches, which is proposed for a fault tolerance technique at the fabrication time. The focus of this paper is to achieve the optimal reconfigurability, which means that whenever there exists a solution for successful reconfiguration, the designed method can find the solution. The paper consists of two parts. In the first part, we show two essential constraints that have been assumed in most of the previous studies, and make four reconfiguration classes that differ in the assumed essential constraints. Then, we present some inclusion relations among the four reconfiguration classes. As a result, it becomes clear that the most restrictive class including most of the previous methods never achieves the truly optimal reconfigurability. In the second part, we present a reconfiguration method based on sequential routing (RMSR). Although the worst-case time complexity of the RMSR is exponential in the number of processing elements, the reconfigurability of the RMSR is optimal within the most restrictive reconfiguration class. The effectiveness of the RMSR is shown by a computer simulation.

We clarify the effectiveness of receiver-side compensation in offsetting fiber Bragg grating (FBG) dispersion induced-electrical signal-to-noise ratio (SNR) degradation in a 10 Gb/s 8-channel wavelength-division multiplexing (WDM) 6,400 km transmission system. The receiver-side compensation greatly improves the SNR degradation. The allowable accumulated FBG dispersion is -400 1000ps/nm for the worst arrangement, a single FBG at the transmitter, which is about half the accumulated fiber dispersion permissible with receiver-side compensation.

A receiver structure, which has linear computational complexity with the number of users, is proposed for decoding multiuser information data in a convolutionally coded asynchronous DS-CDMA system in multipath fading channels. The proposed receiver architecture consists of a multiuser likelihood calculator followed by a bank of soft-input soft-output (SISO) channel decoders. Information is fed back from SISO channel decoders to multiuser likelihood calculator, and the processing proceeds in an iterative fashion analogous to the decoding of turbo codes. A simplification to the above receiver structure is given too. Simulation results demonstrate that for both receiver structures at high signal-to-noise ratios (SNR) both multiple-access interference (MAI) and inter-symbol interference (ISI) are efficiently suppressed, and single-user performance is approached. Furthermore, the proposed iterative receiver is near-far resistant.

In this paper, we propose an efficient quality-providing scheme to satisfy delay bound and loss ratio requirements for real-time video applications. To utilize network resources more efficiently while meeting service requirements, the network resources are dynamically allocated to each video connection based on the predicted traffic and currently provided quality of service degree. With the proposed bandwidth allocation method, a fair quality of service support in terms of packet loss ratio and maximum packet transfer delay to each video source can be achieved. To avoid possible quality violation by incoming new video connections, we present a connection admission control based on the provided QoS for existing connections and the measured traffic statistics. Simulation results show that our proposed dynamic method is able to provide accurate quality control.

This paper evaluates the bit error rate (BER) performance of high rate data transmission such as at 64 and 384 kbits/s (kbps) with high quality (average BER is below 10-6) using turbo/convolutional coding associated with Rake time diversity, antenna diversity, and fast transmission power control (TPC) in multipath fading channels for W-CDMA mobile communications. Laboratory experiments using multipath fading simulators elucidate the superiority of turbo coding over convolutional coding when the channel interleaving length is 40 msec. The required average transmission power for the average BER of 10-6 using turbo coding is decreased by approximately 1.1-1.5 dB and 1.5-1.6 dB for 64 and 384 kbps data transmissions, respectively, compared to that using convolutional coding for a two-path Rayleigh fading channel with the fading maximum Doppler frequency of fD = 5-200 Hz. Furthermore, field experimental results elucidate that the required transmission power for the average BER of 10-6 employing turbo coding is decreased by approximately 0.6 dB and 2.0 dB compared to convolutional coding for 64 and 384 kbps data transmissions, respectively, without antenna diversity reception, while that with antenna diversity reception exhibits only an approximate 0.3-0.5 dB decrease. This decrease in improvement with antenna diversity reception indicates that in an actual fading channel in the field experiments, the impact of the error in path search for Rake combining and SIR measurement for fast TPC diminishes the performance improvement of the turbo coding due to a very low received signal power.

A novel compact T/R (Transmit/Receive) switching circuit for wideband T/R modules has been proposed. It employs quadrature couplers and gate-and-drain-driven HPAs to remove circulators or T/R switches from a conventional T/R module, and T/R switching is made with controlling biasing conditions of the FETs in HPAs. Furthermore, an optimum biasing condition and design of output matching circuit of the HPA have been studied to reduce loss in RX-mode, and the validity of the method has been confirmed by measurements.

As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.

Computing the Eigen Value Decomposition (EVD) of a symmetric matrix is a frequently encountered problem in adaptive (or smart or software) antenna signal processing, for example, super resolution DOA (Direction Of Arrival) estimation algorithms such as MUSIC (MUltiple SIgnal Classification) and ESPRIT (Estimation of Signal Parameters via Rotational Invariance Technique). In this paper the hardware architecture of the fast EVD processor of symmetric correlation matrices for the application of an adaptive antenna technology such as DOA estimation is proposed and the basic idea is also presented. Cyclic Jacobi method is well known for the simplest algorithm and easily implemented but its convergence time is slower than other factorization algorithm like QR-method. But if considering the fast parallel computation of the EVD with a hardware architecture like ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), the Jacobi method can be a appropriate solution, since it offers a quite higher degree of parallelism and easier implementation than other factorization algorithms. This paper computes the EVD using a Jacobi-type method, where the vector rotations and the angles of the rotations are obtained by CORDIC (COordinate Rotation DIgital Computer). The hardware architecture suitable for ASIC or FPGA with fixed-point arithmetic is presented. Because it consists of only shift and add operations, this hardware friendly feature provides easy and efficient implementation. In this paper, the computational load, the estimate of circuit scale and expected performance are discussed and the validation of fixed-point arithmetic for the practical application to MUSIC DOA estimation is examined.

When we use an adaptive array antenna (AAA) with the minimum mean square error (MMSE) criterion under the multipath environment, where the receiving signal level varies, it is difficult for the AAA to converge because of the distortion of the desired wave. Then, we need the equalization both in space and time domains. A tapped-delay-line adaptive array antenna (TDL-AAA) and the AAA with linear equalizer (AAA-LE) have been proposed as simple space-temporal equalization. The AAA-LE has not utilized the recursive least square (RLS) algorithm. In this paper, we propose a space-temporal simultaneous processing equalizer (ST-SPE) that is an AAA-LE with the RLS algorithm. We proposed that the first tap weight of the LE should be fixed and the necessity of that is derived from a normal equation in the MMSE criterion. We achieved the space-temporal simultaneous equalization with the RLS algorithm by this configuration. The ST-SPE can reduce the computational complexity of the space-temporal joint equalization in comparison to the TDL-AAA, when the ST-SPE has almost the same performance as the TDL-AAA in multipath environment with minimum phase condition such as appeared at line-of-sight (LOS).

We suggest a new probe message structure and an efficient probe-based deadlock detection and recovery algorithm that can be used in distributed database systems. We determine the characteristics of the probe messages and suggest an algorithm that can reduce the communication cost required for deadlock detection and recovery.

In this paper, we analyze the convergence and steady-state behavior of the least mean-square (LMS) adaptive filtering algorithm for a finite-length phase-splitting hybrid-type decision feedback equalizer (H-DFE). With some approximations, we derive an iterative expression for the excess mean-square error (MSE) of the H-DFE, which is composed of three statistically dependent excess MSEs; that is, the excess MSEs of the feedforward filter (FFF), intersymbol interference predictive feedback filter (ISI-FBF), and noise predictive feedback filter (NP-FBF) taps. Computer simulation and analytical results show that the average eigenvalue of the input signal for the NP-FBF taps of the H-DFE is time-varying, whereas those for the FFF and ISI-FBF taps are fixed. Nevertheless, the H-DFE can be implemented with fixed step sizes that ensure the convergence of the LMS algorithm without performance degradation from the standpoint of convergence speed, as well as steady-state performance for digital subscriber line (xDSL) applications.