A blind equalizer which uses the differential constant modulus algorithm (DCMA) is introduced. An anchored FIR equalizer applied to a first-order autoregressive channel and updated according to the DCMA is shown to converge to the inverse of that channel regardless of the initial tap-weights and the gain along the direct path.

The progress made in large-scale integration of the baseband circuits of digital cellular phones now makes it possible to implement a voice CODEC and its related functions in the baseband LSI rather than through a general-purpose digital signal processor. This paper describes an improved hardware solution that enables efficient application of the PSI-CELP CODEC-- the most complex CODEC for mobile systems--to the PDC half-rate system through its implementation as a DSP macro in a low-voltage, large-scale LSI. Specific circuit blocks are added as hardware engines to a general-purpose DSP-oriented core. These specific engines were implemented as peripheral circuits for a DSP macro that can be used as a single DSP with an added I/O circuit and is suitable for use in future highly integrated mobile baseband chips. With the assistance of these hardware engines and some additional ALU instructions to achieve efficient programming, the machine speed required for the CODEC can be relatively slow, thus allowing the same architecture to be repeatedly used without needing to set the transistor threshold voltage too low even when the use of deeper sub-micron technologies require a chip to run at a lower supply voltage. We evaluated this DSP-macro architecture using a 0.35 µm CMOS technology test chip. Then we developed a commercial base version using 0.25 µm technology and verified that it can operate at 1.2 V and that the PSI-CELP CODEC can be done at 40 MIPS with power consumption of 11 mW. We also verified that the circuit design can be applied up to 0.18 µm technology with a single threshold voltage of 0.3 V. Thus, the design of the DSP macro incorporating the hardware engines provides a great deal of flexibility that should allow its use in chips based on future technologies and the voice CODEC firmware can be effectively re-used. Although the DSP macro architecture was designed mainly through PSI-CELP application analysis, it can process other voice CODECs such as the AMR CODEC for third-generation mobile applications as well as some other mobile baseband functions such as channel CODECs. This approach can also be refined to permit its application to, for example, high-quality audio CODECs.

We apply newly developed rigorous modal transmission-line theory (MTLT) to evaluate optimal design conditions on optical power coupling in grating-assisted directional couplers (GADCs) with two or three guiding channels. By defining a power distribution ratio (PDR) and coupling efficiency (CE) amenable to the rigorous analytical solutions of MTLT, we explicitly analyze the power coupling characteristics of TE modes propagating in GADCs. The numerical results reveal that the incident power is optimally coupled into the desired guiding channel if the powers of rigorous modes excited at the input boundary of grating-assisted coupler are equally partitioned.

In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.

A problem of obtaining an optimal file transfer of a file transmission net N is to consider how to transmit, with the minimum total cost, copies of a certain file of information from some vertices, called sources, to other vertices of N by the respective vertices' copy demand numbers. This problem is NP-hard for a general file transmission net N. Some classes of N, on each of which a polynomial time algorithm for obtaining an optimal file transfer can be designed, are known. In the characterization, we assumed that file given originally to the source remains at the source without being transmitted. In this paper, we relax the assumption to the one that a sufficient number of copies of the file are given to the source and those copies can be transmitted from the source to other vertices on N. Under this new assumption, we characterize a class of file transmission nets, on each of which a polynomial time algorithm for obtaining an optimal file transfer can be designed. A minimum spanning tree with degree constraints plays a key role in the algorithm.

A postprocessing algorithm is presented for blocking artifact reduction in block-coded images using the adaptive filters along the pattern of neighborhood blocks. Blocking artifacts appear as irregular high-frequency components at block boundaries, thereby reducing the noncorrelation between blocks due to the independent quantization process of each block. Accordingly, block-adaptive filtering is proposed to remove such components and enable similar frequency distributions within two neighborhood blocks and a high correlation between blocks. This type of filtering consists of inter-block filtering to remove blocking artifacts at the block boundaries and intra-block filtering to remove ringing noises within a block. First, each block is classified into one of seven classes based on the characteristics of the DCT coefficient and MV (motion vector) received in the decoder. Thereafter, adaptive intra-block filters, approximated to the normalized frequency distributions of each class, are applied adaptively according to the various patterns and frequency distributions of each block as well as the filtering directions in order to reduce the blocking artifacts. Finally, intra-block filtering is performed on those blocks classified as complex to reduce any ringing noise without blurring the edges. Experimental tests confirmed the effectiveness of the proposed algorithm.

An L-Band high efficiency and low distortion multi-stage amplifier using self phase distortion compensation technique is presented. In this amplifier, the bias condition of the driver-stage transistor is tuned to compensate the phase distortion of the power-stage transistor, and the load and source impedances of the driver-stage and power-stage transistors are optimized to achieve the maximum efficiency with a specified adjacent channel leakage power (ACP) for multi-stage amplifier. The developed amplifier achieves a power added efficiency (Eadd) of 42.8% and an output power (Pout) of 26.8 dBm with an ACP of -38 dBc at 1.95 GHz for wide-band code-division multiple-access (W-CDMA) cellular phones.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay times of long paths are shortened and the delay times of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which is caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of circuit delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.

This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

In this paper, we present a novel algorithm to the alternative wiring problem by analyzing the implication relationship between nodes of alternative wires. Alternative wiring, or rewiring, refers to the process of adding a redundant connection to a circuit so as to make a target connection redundant and removable from the circuit without altering the functionality of the circuit. The well-known ATPG-based alternative wiring scheme, Redundancy Addition and Removal for Multi-level Boolean Optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. But, the deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires. Our approaches of redundancy identification by source node and destination node implication relationship indicate that a large subset of unnecessary redundancy check processes can be further avoided to improve the efficiency significantly. We propose an algorithm, the Implication Based Alternative Wiring Logic Transformation (IBAW), to integrate the two adroit techniques. IBAW provides a competent solution to the alternative wiring problem and shows an outstanding efficiency in our experiments. Experiments were performed on MCNC benchmark circuits. Results show that IBAW runs 6.8 times faster than the original RAMBO in locating alternative wires and solution quality is maintained.

This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).

This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.

A shared binary decision diagram (SBDD) represents a multiple-output function, where nodes are shared among BDDs representing the various outputs. A partitioned SBDD consists of two or more SBDDs that share nodes. The separate SBDDs are optimized independently, often resulting in a reduction in the number of nodes over a single SBDD. We show a method for partitioning a single SBDD into two parts that reduces the node count. Among the benchmark functions tested, a node reduction of up to 23% is realized.

This paper presents architecture design, FPGA implementation, and measurement results of a real-time signal processing circuit for WCDMA uplink baseband receiver. To enhance uplink signal-to-interference-plus-noise ratio (SINR) performance, a four-element antenna array and a four-finger Rake combiner are integrated in the proposed receiver. Moreover, a low-complexity beamforming architecture using a correlator-based beam searcher, a decision-directed carrier synchronization loop, and a matched-filter based channel estimator is also designed. Simulations are based on the standard Doppler-fading scalar channel models provided by 3GPP and an extension to vector channel models that specify angle of arrival for each path is also made for beamformer simulation. Simulation and hardware emulation results show that the proposed architecture meets the specified requirements. In addition, this architecture, with its correlator-based beamformer weights, achieves such performance improvement with relatively low hardware complexity.

A new approach to build up a real-time multiprocessing system that is configuration flexible for evaluating space-time (ST) equalizers is described. The core of the system consists of fully programmable devices such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and reduced instruction set computers (RISCs) with a real-time operating system (RTOS). The RTOS facilitates flexibility in the multi-processor configuration for the system conforming with ST processing algorithms. Timing jitter synchronization caused by use of the RTOS-embedded system is shown, and an adjustable frame format for a transmission system is described as a measure to avoid the jitter problem. Bit error rate (BER) performances measured in uncorrelated frequency-selective fading channels show that an ST equalizer provides a significantly lower BER than an array processor does.

We clarify the effectiveness of receiver-side compensation in offsetting fiber Bragg grating (FBG) dispersion induced-electrical signal-to-noise ratio (SNR) degradation in a 10 Gb/s 8-channel wavelength-division multiplexing (WDM) 6,400 km transmission system. The receiver-side compensation greatly improves the SNR degradation. The allowable accumulated FBG dispersion is -400 1000ps/nm for the worst arrangement, a single FBG at the transmitter, which is about half the accumulated fiber dispersion permissible with receiver-side compensation.

This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.

In an orthogonal frequency division multiplexing (OFDM) system, the bit error performance is degraded in the presence of multiple propagation paths whose excess delays are longer than the Guard Interval (GI), because the orthogonality between subcarriers cannot be maintained. In this paper, we propose a new OFDM demodulation method with a variable-length effective symbol and a multi-stage inter-carrier interference (ICI) canceller, in order to improve the bit error performance in the presence of multipaths whose excess delays are longer than the GI. The influence of the inter-symbol interference (ISI) is eliminated by the variable-length effective symbol, and then the ICI component is reduced by the multi-stage ICI canceller. The principle of the proposed method is explained, and the performance of the proposed method is then evaluated by computer simulation. The results show that the proposed method improves the system availability under more various multipath fading environments without changing the system parameters.