We demonstrate a simple BER monitoring method for WDM signals. Newly developed 32-channel wavelength selector based on thermo-optic switch and AWG is used. The BER of each channel is estimated from opened eye-diagrams obtained by asynchronous sampling. Good BER monitoring performance is confirmed.

A new algorithm and architecture to eliminate redundant operations in block-matching (BM) motion estimation is proposed. The key step of this work is to use binary-matching to define image regions with the static background content and then exclude these regions from the actual motion estimation. According to experiments, the approach maintains the highest PSNR, while making as half as less computations in comparison to the adaptive BM or 1/8 of the computations required by the full-search BM. An implementation scheme is outlined.

This paper introduces a power-efficient on-chip DC-DC converter, which produces a 1.0 V output by being stepped-down from a 3.6 V input, utilizes a 10 µH external inductor, and realizes more than 80% power-efficiency. In order to realize a 1.0 V output without decreasing power-efficiency, a synchronous-type rectifier scheme with a reverse current protection circuit is adopted and a reference voltage of less than 1.0 V is developed. The external inductor value is reduced by applying the PWM control scheme and a new low-power 1 MHz triangular waveform oscillator. High-value resistors are used in analog circuits including a voltage reference, a triangular waveform oscillator, an error amplifier, and a comparator to have the ultra-low power characteristics. A chip is actually designed and fabricated by using the 2 µm CMOS process. As a result, a 1 MHz, synchronous, step-down from 3.6 V to 1 V, PWM DC-DC converter has been realized with a power efficiency of more than 80% in the output current range from 40 to 70 mA.

Conventional vector quantization (VQ) encoding method by full search (FS) is very heavy computationally but it can reach the best PSNR. In order to speed up the encoding process, many fast search methods have been developed. Base on the concept of multi-resolutions, the FS equivalent fast search methods using mean-type pyramid data structure have been proposed already in. In this Letter, an enhanced sum pyramid data structure is suggested to improve search efficiency further, which benefits from (1) exact computing in integer form, (2) one more 2-dimensional new resolution and (3) an optimal pair selecting way for constructing the new resolution. Experimental results show that a lot of codewords can be rejected efficiently by using this added new resolution that features lower dimensions and earlier difference check order.

A real-time frame-layer rate control algorithm using sliding window method is proposed for low bit rate video coding over the Internet. The proposed rate control method performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. A new frame-layer rate-distortion model is derived, and a non-iterative optimization method is used for low computational complexity. In order to reduce the quality fluctuation, we use a sliding window scheme which does not require the pre-analysis process. Therefore, the proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performance than the existing TMN8 rate control method.

A new sorting algorithm and architecture for fast median filter are proposed. This algorithm results in low area VLSI architecture producing low switching activity and without using feedback. The main idea is to employ the extra matrix for fast search operation of rank of oldest window element. We simulated and synthesized this algorithm using SYNOPSYSTM and showed the sufficiency in real time operation.

Streaming services and visual communication services delivered over the Internet have become popular in recent years. In the future, broadband services using MPEG2/4 will become the dominant type. These services will require transport protocols that provide high quality and high throughput from end to end of the system. We propose a new transfer method that allows the network load to be adaptively balanced according to the network's state. We built a prototype of an actual MPEG2 streaming system and used it to estimate the effectiveness of this method.

This paper presents a computationally efficient subspace-based method for partially adaptive beamforming which is based on the structure of the generalized sidelobe canceller (GSC). Its auxiliary beamformer operates in an estimated interference subspace which is obtained through simple computation. The computational burden of the proposed method in terms of complex multiplication is just on O(η2M) where η and M are the numbers of interferences and the array elements, respectively. Though the subspace obtained is different from the exact interference subspace due to the presence of noise, theoretical analysis shows that the proposed beamfomer virtually attains the optimal performance for strong or sidelobe interference. Simulation results validate its effectiveness including fast convergence, even in the presence of errors in the detected number of directional signals.

A novel modified midtread quantizer is proposed for number-controlled oscillator frequency quantization in digital phase-locked loops (DPLLs). We show that DPLLs employing the proposed quantizer provide significantly improved cycle slip performance compared to those employing conventional midtread or midrise quantizers, especially when the number of quantization bits is small and the magnitude of input signal frequency normalized by the quantization interval is less than 0.5.

In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

We have designed, fabricated and characterized efficient optical resonators and low-threshold lasers based on planar photonic crystal concept. Lasers with InGaAsP quantum well active material emitting at 1550 nm were optically pumped, and room temperature lasing was observed at threshold powers below 220 µW. Porous high quality factor cavity that we have developed confines light in the air region and therefore our lasers are ideally suited for investigation of interaction between light and matter on a nanoscale level. We have demonstrated the operation of photonic crystal lasers in different ambient organic solutions, and we have showed that planar photonic crystal lasers can be used to perform spectroscopic tests on femtoliter volumes of analyte.

This paper proposes a new supply current test method for detecting floating gate defects in CMOS ICs. In the method, unusual increase of the supply current caused by defects is promoted by superposing an AC component on the DC power supply. Feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional supply current test.

This paper studies the propagation and crossing of signals in cellular automata whose cells are updated at random times. The signals considered consist of a core part, surrounded by an insulating sheath that is missing at the side of the core that corresponds to the direction into which the signal moves. We study two types of signals: (1) signals by which the sheath at the left and right sides of the core advance first in a propagation step, followed by the core, and (2) signals by which the core advances first, followed by the sheath at its left and right sides. These types naturally arise in, respectively, Moore neighborhood cellular automata with semi-totalistic rules and von Neumann neighborhood cellular automata with symmetric transition rules. The type of a signal has a profound impact on the way signals cross each other, as we show by the construction of one signal of each type. The results we obtained should be of assistance in constructing asynchronous circuits on asynchronous cellular automata.

This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.

The partially rotational scan (PRS) technique greatly reduces the amount of data needed for n-detection testing. It also enables at-speed testing using low-speed testers. We designed tester intellectual properties (tester IP) with PRS for Viper and COMET II processors. When PRS was applied to a Viper processor, we obtained test data that provided the same fault coverage as with a set of automatic test pattern generation (ATPG) test vectors, although the amount of test data was 16% that of the ATPG. When the PRS technique was applied to a COMET II processor with full-scan design, we obtained test data that provided the same fault coverage as with a set of ATPG test vectors, although the amount of test data was 10% that of the ATPG. We also estimated hardware overhead and test time.

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may occur in the circuit. In this paper, some electrical conditions are proposed to identify whether a feedback bridging fault occurs logical oscillation. Also, it is proposed how to estimate the oscillation frequency. They are based on piece linearlized models and do not require circuit simulation of large size of circuits. They are evaluated by some experiments. In the experiments, all of the feedback bridging faults occurring logical oscillation are identified. Also, oscillation frequencies larger than the ones obtained by SPICE simulation are derived by the proposed estimation method in the experiments. It promises us that the methods will be used for identifying such bridging faults and estimating the oscillation frequencies.

In this paper, we analyze behaviors of bridging faults in CMOS synchronous sequential circuits based on transient analysis. From analysis results, we expose dynamic and analog behaviors of the circuit caused by the bridging faults, which are oscillation, asynchronous sequential behavior, IDDT failure and IDDQ failure as well as logic error. In order to detect this kind of fault, we show that not only IDDQ testing but also IDDT testing and logic testing which guarantees correct state transitions are required.

This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.

In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.

Mining generalized frequent patterns of generalized association rules is an important process in knowledge discovery system. In this paper, we propose a new approach for efficiently mining all frequent patterns using a novel set enumeration algorithm with two types of constraints on two generalized itemset relationships, called subset-superset and ancestor-descendant constraints. We also show a method to mine a smaller set of generalized closed frequent itemsets instead of mining a large set of conventional generalized frequent itemsets. To this end, we develop two algorithms called SET and cSET for mining generalized frequent itemsets and generalized closed frequent itemsets, respectively. By a number of experiments, the proposed algorithms outperform the previous well-known algorithms in both computational time and memory utilization. Furthermore, the experiments with real datasets indicate that mining generalized closed frequent itemsets gains more merit on computational costs since the number of generalized closed frequent itemsets is much more smaller than the number of generalized frequent itemsets.