We study analysis of hybrid systems under incomplete knowledge. The class of hybrid systems to be considered is assumed to have the form of a rectangular hybrid automaton such that each constant in invariants and guards is given as a parameter. We develop a method based on symbolic computation that computes an approximation of the discrete behavior of the automaton. We also show an implementation on a constraint logic programming language.

In this paper we present a new type of CMOS Time-of-Flight (TOF) range image sensor based on CMOS Active Pixel Sensor (APS) techniques. The TOF sensor features high-speed and efficient photo-charge transfer that is essential in range imaging. The rapid and efficient charge transfer is made possible by the use of a high-gain inverting amplifier and capacitors connected alternatively to the feedback path. This leads to the cost-effective implementation of the system. The analysis of simulation results suggests that the proposed technique can achieve a sufficient range resolution of millimeters to centimeters depending on the maximum measured range, if the noise is dominated by photon shot noise.

A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.

An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 360 µm2 and 240 280 µm2, respectively.

This paper presents an asynchronous data transfer scheme using 2-color 2-phase dual-rail encoding based on a differential operation and its circuit realization. The proposed encoding enables seamless asynchronous data transfer without inserting a spacer, because each logic value is represented by two kinds of codewords with dual-rail, called "color" data. Since the difference x-x between components of a codeword (x,x) becomes constant in every valid state, the data-arrival state can be detected by calculating the difference x-x. From the viewpoint of circuit implementation, during the state transition, since the dual-rail x and x are defined so as to transit differentially, the compatibility with a comparator using a differential amplifier becomes high, which results in reduction of the cycle time. It is evaluated using HSPICE simulation with a 0.18 µm CMOS technology that communication speed using the proposed dual-rail encoding becomes 1.4 times faster than that using conventional dual-rail encoding.

Ultrahigh-speed compact flash analog-to-digital converters (ADCs) using resonant-tunneling diodes (RTDs) have been designed to demonstrate a high potential of RTD circuits. Novel multi-input subtraction gates are introduced to the encoder to obtain a compact circuit configuration. By assuming 0.1-µm InP-based RTD/HEMT technology, circuit simulations of 4-bit 10-GHz flash ADCs are carried out. It is found that the device counts of the ADC with an 8-input gate are one third that of the ADC with 4-input gates. This leads to a reduction in the power dissipation by 50%. In addition, bandwidths of more than 20 GHz have been obtained for 4-bit and 5-bit ADCs at a sampling frequency of 10 GHz.

In this paper, we consider the problem of multicast routing and wavelength assignment (MC-RWA) in multi-fiber all-optical WDM networks. Two main network design system comprehensively investigated here are mesh and multi-ring designs. Given the multicast traffic demands, we present new ILP formulations to solve the MC-RWA problem with an objective to determine the minimal number of fibers needed to support the multicast requests. Unlike previous studies, our ILP formulations are not only capable of finding the optimal multicast routing and wavelength assignment pattern to the light-trees, but also finding the optimal light-tree structures simultaneously. Since broadcast and unicast communications are special cases of multicast communications, our ILP models are actually the generalized RWA mathematical models of optical WDM networks. In addition to proposing the ILP models, this paper takes two main issues affecting the network capacity requirement into account, that is, the splitting degree level of optical splitters and techniques of wavelength assignment to the light-trees. Three multicast wavelength assignment techniques studied in this paper are Light-Tree (LT), Virtual Light-Tree (VLT) and Partial Virtual Light-Tree (PVLT) techniques. Due to the NP-completeness of the MC-RWA problem, the ILP formulations can reasonably cope with small and moderate networks. To work with large networks, this paper presents alternative MC-RWA ILP-based heuristic algorithms for the PVLT and LT networks and develops lower bound techniques to characterize the performance of our algorithms. Using existing large backbone networks, numerical results are reported to analyze such aspects as multiple fiber systems, the benefits of using optical splitters and wavelength converters, and the capacity difference between the mesh and multi-ring designs. Finally, this paper provides an analysis of the influence of network connectivity on the network implementation under the constraints of mesh and multi-ring design schemes.

In this paper, a new computing paradigm suitable for analog circuit systems is described in comparison to the digital circuit systems. The analog circuit systems have some disadvantages especially in terms of accuracy and stability, but there are some applications that don't require accuracy or stability in circuit component. The new computing concept for such applications, 'inaccurate' information processing, or 'rough' information processing, is proposed and described as well as some examples of such applications.

In this paper, we term multimedia streaming application traffic "stream flows" and the other usual application traffic "non-stream flows." Many problems occur when both flows are aggregated on a shared link because the different TCP and UDP behaviors cause negative interactions. One way to solve these problems is to isolate stream and non-stream flows to different classes. However, it is difficult to determine the bandwidth allocation for each class and dynamic bandwidth allocation schemes are hard to implement on large scale networks. We therefore propose a dynamic class assignment method that maintains the QoS and that has a higher scalability than dynamic bandwidth allocation schemes. It is workable on Diffserv AF PHB. The outline is as follows. We classify non-stream flows into four classes and dynamically assign stream flows to the classes, taking the conditions and characteristics of the classes into consideration. On assigning classes to stream flows, we map them to a higher drop precedence than non-stream flows not to degrade the QoS of them, based on the assumption that occasional packets being dropped do not create serious problems for them. In this paper, we first discuss our classification of non-stream flows, and present the characteristics of non-stream flows in each class. We then discuss our drop precedence mapping. After this, we propose an algorithm for our method of dynamic class assignment and provide some simulation results where it could provide constant qualities with stream and non-stream flows, adapting to changing traffic.

Active Reliable Multicast (ARM) is a novel loss recovery scheme for large-scale reliable multicast that employs active routers to protect the sender and network bandwidth from unnecessary feedback and repair traffic. Active routers perform NACKs suppression, cache multicast data for local loss recovery, and use scoped retransmission to avoid exposure. Limited active resources at routers need to be optimized to achieve low loss recovery latency and/or high network throughput. In this paper, we study the cache placement strategies and caching policies for ARM. Several heuristics, namely uniform allocation, proportional allocation, max-min fair share and weighted allocation for cache allocation methods are proposed. To further improve the loss recovery performance, caching policies can be employed in conjunction with the cache allocation strategies. Several caching policies, namely complete caching, random caching and deterministic caching, are proposed. Extensive simulation experiments are conducted to evaluate and compare the performance of the proposed strategies and policies. Numerical results reveal that significant performance gains can be achieved when a proper cache placement strategy and a caching policy are used for a given available cache resource. Another interesting finding is that the contributions of the cache placement scheme and caching policy to the recovery latency performance are roughly independent. The obtained insights in this study will provide some design guidelines for optimal active resource allocation and caching polices for reliable multicast communications.

This paper presents a multi-resolution optical flow estimation method that is robust against large variation in the estimation parameter. For each level solution of the multi-grid estimation, a nonlinear iteration is proposed differently from the existing method, where the incremental displacement from the coarser level optical flow is calculated by linear iteration. The experimental results show that the proposed scheme has better error-performance in a much wider range of regularization parameters.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

A low-power high-frequency sinusoidal quadrature oscillator is presented through a new RC technique using only CMOS current mirrors. The technique is relatively simple based on (1) internal capacitances of CMOS current mirrors and (2) a resistor of a CMOS current mirror for a negative resistance. Neither external capacitances nor inductances are required. As a particular example, a 2.4 GHz-0.4 mW, 0.325-fT, CMOS sinusoidal quadrature oscillator has been demonstrated. The power consumption is very low at approximately 0.4 mW. Total harmonic distortions (THD) are less than 0.3%. The oscillation frequency is current-tunable over a range of 540 MHz or 22%. The amplitude matching and the quadrature phase matching are better than 0.035 dB and 0.15, respectively. A figure of merit called a normalized carrier-to-noise ratio (CNRnorm) is 158.79 dBc/Hz at the 2 MHz offset from 2.46 GHz. Comparisons to other approaches are also presented.

This paper proposes a simple method for estimation and compensation of signal direction, to deal with relative change of sound source location caused by the movements of a microphone array and a sound source. This method introduces a delay filter that has shifted and sampled sinc functions. This paper presents a concept for the joint optimization of arrival time differences and of the coordinate system of a mobile microphone array. We use the LMS algorithm to derive this method by maintaining a certain relationship between the directions of the microphone array and the sound source directions. This method directly estimates the relative directions of the microphone array to the sound source directions by minimizing the relative differences of arrival time among the observed signals, not by estimating the time difference of arrival (TDOA) between two observed signals. This method also compensates the time delay of the observed signals simultaneously, and it has a feature to maintain that the output signals are in phase. Simulation results support effectiveness of the method.

The relation between resonant frequency of micromirror with vertical combdrives and applied voltage between the upper and lower comb teeth was analyzed. Resonant frequency of the micromirror was controlled by stiffness of the torsion hinge. Resonant frequency of the mirror was proportional to the applied voltage between the upper and lower comb teeth at the same tilt angle.

For large circuits, vector compaction techniques could provide a faster solution for power estimation with reasonable accuracy. Because traditional sampling approach will incur useless transitions between every sampled pattern pairs after they are concatenated into a single sequence for simulation, we proposed a vector compaction method with grouping and single-sequence consecutive sampling technique to solve this problem. However, it is very possible that we cannot find a perfect consecutive sequence without any undesired transitions. In such cases, the compaction ratio of the sequence length may not be improved too much. In this paper, we propose an efficient approach to relax the limitation a little bit such that multiple consecutive sequences are allowed. We also propose an algorithm to reduce the number of sequences instead of setting the number as one to find better solutions for vector compaction problem. As demonstrated in the experimental results, the average compaction ratio and speedup can be significantly improved by using this new approach.

This paper investigates a random-interleaver-based approach to space-time coding. The basic principle is to employ a good forward error correction (FEC) code and transmit randomly interleaved codewords over an antenna array. A low-cost estimation technique is considered. The complexity involved grows only linearly with the number of transmit antennas. Near-capacity performance can be achieved with moderate complexity.

This letter presents a novel video and audio PTSs self-adaptive interlace strategy in MPEG-2 transport stream. By adaptive regulating the relative position of audio and video access units in bit-stream according to their PTSs, the proposed strategy provides reliable video and audio synchronization.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

This paper considers a motion planning method for humanoid robots. First, we review a modular state net which is a state net representing behavior of a part of the humanoid robots. Each whole body motion of the humanoid robots is represented by a combination of modular state nets for those parts. In order to obtain a feasible path of the whole body, a timed Petri net is used as an abstracted model of a set of all modular state nets. Next, we show an algorithm for constructing nonlinear dynamics which describes a periodic motion. Finally, we extend the state net in order to represent primitive periodic motions and their transition relation so that we can generate a sequence of primitive periodic motions satisfying a specified task.