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Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices

Yusuke YANO, Kengo IOKIBE, Toshiaki TESHIMA, Yoshitaka TOYOTA, Toshihiro KATASHITA, Yohei HORI

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Summary :

Side-channel (SC) leakage from a cryptographic device chip is simulated as the dynamic current flowing out of the chip. When evaluating the simulated current, an evaluation by comparison with an actual measurement is essential; however, it is difficult to compare them directly. This is because a measured waveform is typically the output voltage of probe placed at the observation position outside the chip, and the actual dynamic current is modified by several transfer impedances. Therefore, in this paper, the probe voltage is converted into the dynamic current by using an EMC macro-model of a cryptographic device being evaluated. This paper shows that both the amplitude and the SC analysis (correlation power analysis and measurements to disclosure) results of the simulated dynamic current were evaluated appropriately by using the EMC macro-model. An evaluation confirms that the shape of the simulated current matches the measured one; moreover, the SC analysis results agreed with the measured ones well. On the basis of the results, it is confirmed that a register-transfer level (RTL) simulation of the dynamic current gives a reasonable estimation of SC traces.

Publication
IEICE TRANSACTIONS on Communications Vol.E104-B No.2 pp.178-186
Publication Date
2021/02/01
Publicized
2020/08/06
Online ISSN
1745-1345
DOI
10.1587/transcom.2020EBP3015
Type of Manuscript
PAPER
Category
Electromagnetic Compatibility(EMC)

Authors

Yusuke YANO
  Okayama University
Kengo IOKIBE
  Okayama University
Toshiaki TESHIMA
  Okayama University
Yoshitaka TOYOTA
  Okayama University
Toshihiro KATASHITA
  National Institute of Advanced Industrial Science and Technology
Yohei HORI
  National Institute of Advanced Industrial Science and Technology

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