To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm
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Kyoya TAKANO, Mizuki MOTOYOSHI, Minoru FUJISHIMA, "4.8 GHz CMOS Frequency Multiplier Using Subharmonic Pulse-Injection Locking for Spurious Suppression" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 11, pp. 1738-1743, November 2008, doi: 10.1093/ietele/e91-c.11.1738.
Abstract: To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.11.1738/_p
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@ARTICLE{e91-c_11_1738,
author={Kyoya TAKANO, Mizuki MOTOYOSHI, Minoru FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={4.8 GHz CMOS Frequency Multiplier Using Subharmonic Pulse-Injection Locking for Spurious Suppression},
year={2008},
volume={E91-C},
number={11},
pages={1738-1743},
abstract={To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm
keywords={},
doi={10.1093/ietele/e91-c.11.1738},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - 4.8 GHz CMOS Frequency Multiplier Using Subharmonic Pulse-Injection Locking for Spurious Suppression
T2 - IEICE TRANSACTIONS on Electronics
SP - 1738
EP - 1743
AU - Kyoya TAKANO
AU - Mizuki MOTOYOSHI
AU - Minoru FUJISHIMA
PY - 2008
DO - 10.1093/ietele/e91-c.11.1738
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2008
AB - To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm
ER -