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A Simple Mechanism for Collapsing Instructions under Timing Speculation

Toshinori SATO

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Summary :

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.

Publication
IEICE TRANSACTIONS on Electronics Vol.E91-C No.9 pp.1394-1401
Publication Date
2008/09/01
Publicized
Online ISSN
1745-1353
DOI
10.1093/ietele/e91-c.9.1394
Type of Manuscript
Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
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