This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.
Takeshi KUMAKI
Masakatsu ISHIZAKI
Tetsushi KOIDE
Hans Jurgen MATTAUSCH
Yasuto KURODA
Takayuki GYOHTEN
Hideyuki NODA
Katsumi DOSAKA
Kazutami ARIMOTO
Kazunori SAITO
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Takeshi KUMAKI, Masakatsu ISHIZAKI, Tetsushi KOIDE, Hans Jurgen MATTAUSCH, Yasuto KURODA, Takayuki GYOHTEN, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Kazunori SAITO, "Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1409-1418, September 2008, doi: 10.1093/ietele/e91-c.9.1409.
Abstract: This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1409/_p
Copy
@ARTICLE{e91-c_9_1409,
author={Takeshi KUMAKI, Masakatsu ISHIZAKI, Tetsushi KOIDE, Hans Jurgen MATTAUSCH, Yasuto KURODA, Takayuki GYOHTEN, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Kazunori SAITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor},
year={2008},
volume={E91-C},
number={9},
pages={1409-1418},
abstract={This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.},
keywords={},
doi={10.1093/ietele/e91-c.9.1409},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1409
EP - 1418
AU - Takeshi KUMAKI
AU - Masakatsu ISHIZAKI
AU - Tetsushi KOIDE
AU - Hans Jurgen MATTAUSCH
AU - Yasuto KURODA
AU - Takayuki GYOHTEN
AU - Hideyuki NODA
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
AU - Kazunori SAITO
PY - 2008
DO - 10.1093/ietele/e91-c.9.1409
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.
ER -