The search functionality is under construction.
The search functionality is under construction.

Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI

Tetsuhisa MIDO, Hiroshi ITO, Kunihiro ASADA

  • Full Text Views

    0

  • Cite this

Summary :

A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.

Publication
IEICE TRANSACTIONS on Electronics Vol.E82-C No.4 pp.570-575
Publication Date
1999/04/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category

Authors

Keyword