A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Tetsuhisa MIDO, Hiroshi ITO, Kunihiro ASADA, "Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 4, pp. 570-575, April 1999, doi: .
Abstract: A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_4_570/_p
Copy
@ARTICLE{e82-c_4_570,
author={Tetsuhisa MIDO, Hiroshi ITO, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI},
year={1999},
volume={E82-C},
number={4},
pages={570-575},
abstract={A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 570
EP - 575
AU - Tetsuhisa MIDO
AU - Hiroshi ITO
AU - Kunihiro ASADA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1999
AB - A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.
ER -