Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.
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Makoto IMAI, Toshiyuki NOZAWA, Masanori FUJIBAYASHI, Koji KOTANI, Tadahiro OHMI, "Fast Computational Architectures to Decrease Redundant Calculations -- Eliminating Redundant Digit Calculation and Excluding Useless Data" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1707-1714, September 1999, doi: .
Abstract: Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1707/_p
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@ARTICLE{e82-c_9_1707,
author={Makoto IMAI, Toshiyuki NOZAWA, Masanori FUJIBAYASHI, Koji KOTANI, Tadahiro OHMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fast Computational Architectures to Decrease Redundant Calculations -- Eliminating Redundant Digit Calculation and Excluding Useless Data},
year={1999},
volume={E82-C},
number={9},
pages={1707-1714},
abstract={Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Fast Computational Architectures to Decrease Redundant Calculations -- Eliminating Redundant Digit Calculation and Excluding Useless Data
T2 - IEICE TRANSACTIONS on Electronics
SP - 1707
EP - 1714
AU - Makoto IMAI
AU - Toshiyuki NOZAWA
AU - Masanori FUJIBAYASHI
AU - Koji KOTANI
AU - Tadahiro OHMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.
ER -