The search functionality is under construction.
The search functionality is under construction.

Fast Computational Architectures to Decrease Redundant Calculations -- Eliminating Redundant Digit Calculation and Excluding Useless Data

Makoto IMAI, Toshiyuki NOZAWA, Masanori FUJIBAYASHI, Koji KOTANI, Tadahiro OHMI

  • Full Text Views

    0

  • Cite this

Summary :

Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.

Publication
IEICE TRANSACTIONS on Electronics Vol.E82-C No.9 pp.1707-1714
Publication Date
1999/09/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category
Processors

Authors

Keyword