A surface extraction algorithm with NURBS has been developed for the mesh generation from the scattered data after a cell-based simulation. The triangulation of a surface is initiated with a step of describing the geometry along the polygonal boundary with multiple points. In this work, an NURBS surface can be generated with scattered data for each polygonal surface by employing a multilevel B-spline surface approximation. The NURBS mesh in accordance with our algorithm excellently represents the surface evolution of the topography on the wafer. A dynamically allocated topography model, so-called cell advancing model, is proposed to resolve an extensive memory requirement for the numerical simulation of a complicated structure on the wafer. A concave cylindrical DRAM cell capacitor was chosen to test the capability of our model. A set of capacitance present in the cell capacitor and interconnects was calculated with three-dimensional tetrahedral meshes generated from the NURBS surface on CRAY T3E supercomputer. A total of 5,475,600 (130
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Sangho YOON, Jaehee LEE, Sukin YOON, Ohseob KWON, Taeyoung WON, "An Advancing Front Meshing Algorithm Using NURBS for Semiconductor Process Simulation" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 8, pp. 1349-1355, August 2000, doi: .
Abstract: A surface extraction algorithm with NURBS has been developed for the mesh generation from the scattered data after a cell-based simulation. The triangulation of a surface is initiated with a step of describing the geometry along the polygonal boundary with multiple points. In this work, an NURBS surface can be generated with scattered data for each polygonal surface by employing a multilevel B-spline surface approximation. The NURBS mesh in accordance with our algorithm excellently represents the surface evolution of the topography on the wafer. A dynamically allocated topography model, so-called cell advancing model, is proposed to resolve an extensive memory requirement for the numerical simulation of a complicated structure on the wafer. A concave cylindrical DRAM cell capacitor was chosen to test the capability of our model. A set of capacitance present in the cell capacitor and interconnects was calculated with three-dimensional tetrahedral meshes generated from the NURBS surface on CRAY T3E supercomputer. A total of 5,475,600 (130
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_8_1349/_p
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@ARTICLE{e83-c_8_1349,
author={Sangho YOON, Jaehee LEE, Sukin YOON, Ohseob KWON, Taeyoung WON, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Advancing Front Meshing Algorithm Using NURBS for Semiconductor Process Simulation},
year={2000},
volume={E83-C},
number={8},
pages={1349-1355},
abstract={A surface extraction algorithm with NURBS has been developed for the mesh generation from the scattered data after a cell-based simulation. The triangulation of a surface is initiated with a step of describing the geometry along the polygonal boundary with multiple points. In this work, an NURBS surface can be generated with scattered data for each polygonal surface by employing a multilevel B-spline surface approximation. The NURBS mesh in accordance with our algorithm excellently represents the surface evolution of the topography on the wafer. A dynamically allocated topography model, so-called cell advancing model, is proposed to resolve an extensive memory requirement for the numerical simulation of a complicated structure on the wafer. A concave cylindrical DRAM cell capacitor was chosen to test the capability of our model. A set of capacitance present in the cell capacitor and interconnects was calculated with three-dimensional tetrahedral meshes generated from the NURBS surface on CRAY T3E supercomputer. A total of 5,475,600 (130
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - An Advancing Front Meshing Algorithm Using NURBS for Semiconductor Process Simulation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1349
EP - 1355
AU - Sangho YOON
AU - Jaehee LEE
AU - Sukin YOON
AU - Ohseob KWON
AU - Taeyoung WON
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2000
AB - A surface extraction algorithm with NURBS has been developed for the mesh generation from the scattered data after a cell-based simulation. The triangulation of a surface is initiated with a step of describing the geometry along the polygonal boundary with multiple points. In this work, an NURBS surface can be generated with scattered data for each polygonal surface by employing a multilevel B-spline surface approximation. The NURBS mesh in accordance with our algorithm excellently represents the surface evolution of the topography on the wafer. A dynamically allocated topography model, so-called cell advancing model, is proposed to resolve an extensive memory requirement for the numerical simulation of a complicated structure on the wafer. A concave cylindrical DRAM cell capacitor was chosen to test the capability of our model. A set of capacitance present in the cell capacitor and interconnects was calculated with three-dimensional tetrahedral meshes generated from the NURBS surface on CRAY T3E supercomputer. A total of 5,475,600 (130
ER -