We propose a vector-pipeline processor VP-DSP for low-rate videophones which can encode and decode 10 frames/sec. of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 µm CMOS process. The area of the VP-DSP core is 4.26 mm2. It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.
Kazutoshi KOBAYASHI
Makoto EGUCHI
Takuya IWAHASHI
Takehide SHIBAYAMA
Xiang LI
Kosuke TAKAI
Hidetoshi ONODERA
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Kazutoshi KOBAYASHI, Makoto EGUCHI, Takuya IWAHASHI, Takehide SHIBAYAMA, Xiang LI, Kosuke TAKAI, Hidetoshi ONODERA, "A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 193-201, February 2001, doi: .
Abstract: We propose a vector-pipeline processor VP-DSP for low-rate videophones which can encode and decode 10 frames/sec. of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 µm CMOS process. The area of the VP-DSP core is 4.26 mm2. It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_193/_p
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@ARTICLE{e84-c_2_193,
author={Kazutoshi KOBAYASHI, Makoto EGUCHI, Takuya IWAHASHI, Takehide SHIBAYAMA, Xiang LI, Kosuke TAKAI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones},
year={2001},
volume={E84-C},
number={2},
pages={193-201},
abstract={We propose a vector-pipeline processor VP-DSP for low-rate videophones which can encode and decode 10 frames/sec. of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 µm CMOS process. The area of the VP-DSP core is 4.26 mm2. It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
T2 - IEICE TRANSACTIONS on Electronics
SP - 193
EP - 201
AU - Kazutoshi KOBAYASHI
AU - Makoto EGUCHI
AU - Takuya IWAHASHI
AU - Takehide SHIBAYAMA
AU - Xiang LI
AU - Kosuke TAKAI
AU - Hidetoshi ONODERA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - We propose a vector-pipeline processor VP-DSP for low-rate videophones which can encode and decode 10 frames/sec. of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 µm CMOS process. The area of the VP-DSP core is 4.26 mm2. It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.
ER -