Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Junji KOGA, Akira TORIUMI, "Silicon Planar Esaki Diode Operating at Room Temperature" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1051-1055, August 2001, doi: .
Abstract: Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1051/_p
Copy
@ARTICLE{e84-c_8_1051,
author={Junji KOGA, Akira TORIUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Silicon Planar Esaki Diode Operating at Room Temperature},
year={2001},
volume={E84-C},
number={8},
pages={1051-1055},
abstract={Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - Silicon Planar Esaki Diode Operating at Room Temperature
T2 - IEICE TRANSACTIONS on Electronics
SP - 1051
EP - 1055
AU - Junji KOGA
AU - Akira TORIUMI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.
ER -