Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.
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Yukinori ONO, Kenji YAMAZAKI, Yasuo TAKAHASHI, "Si Single-Electron Transistors with High Voltage Gain" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1061-1065, August 2001, doi: .
Abstract: Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1061/_p
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@ARTICLE{e84-c_8_1061,
author={Yukinori ONO, Kenji YAMAZAKI, Yasuo TAKAHASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Si Single-Electron Transistors with High Voltage Gain},
year={2001},
volume={E84-C},
number={8},
pages={1061-1065},
abstract={Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Si Single-Electron Transistors with High Voltage Gain
T2 - IEICE TRANSACTIONS on Electronics
SP - 1061
EP - 1065
AU - Yukinori ONO
AU - Kenji YAMAZAKI
AU - Yasuo TAKAHASHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.
ER -