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This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.3 pp.595-598

- Publication Date
- 2002/03/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section LETTER (Special Issue on Signals, Systems and Electronics Technology)

- Category

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Ken'ichi TAJIMA, Yoshihiko IMAI, Yousuke KANAGAWA, Kenji ITOH, Yoji ISOTA, Osami ISHIDA, "Low Spurious Frequency Setting Algorithm for a Triple Tuned Type PLL Synthesizer Driven by a DDS" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 3, pp. 595-598, March 2002, doi: .

Abstract: This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_3_595/_p

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@ARTICLE{e85-c_3_595,

author={Ken'ichi TAJIMA, Yoshihiko IMAI, Yousuke KANAGAWA, Kenji ITOH, Yoji ISOTA, Osami ISHIDA, },

journal={IEICE TRANSACTIONS on Electronics},

title={Low Spurious Frequency Setting Algorithm for a Triple Tuned Type PLL Synthesizer Driven by a DDS},

year={2002},

volume={E85-C},

number={3},

pages={595-598},

abstract={This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.},

keywords={},

doi={},

ISSN={},

month={March},}

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TY - JOUR

TI - Low Spurious Frequency Setting Algorithm for a Triple Tuned Type PLL Synthesizer Driven by a DDS

T2 - IEICE TRANSACTIONS on Electronics

SP - 595

EP - 598

AU - Ken'ichi TAJIMA

AU - Yoshihiko IMAI

AU - Yousuke KANAGAWA

AU - Kenji ITOH

AU - Yoji ISOTA

AU - Osami ISHIDA

PY - 2002

DO -

JO - IEICE TRANSACTIONS on Electronics

SN -

VL - E85-C

IS - 3

JA - IEICE TRANSACTIONS on Electronics

Y1 - March 2002

AB - This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

ER -