We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.
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Lizhen ZHENG, Xiaofan MENG, Stephen WHITELEY, Theodore Van DUZER, "50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 3, pp. 621-624, March 2002, doi: .
Abstract: We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_3_621/_p
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@ARTICLE{e85-c_3_621,
author={Lizhen ZHENG, Xiaofan MENG, Stephen WHITELEY, Theodore Van DUZER, },
journal={IEICE TRANSACTIONS on Electronics},
title={50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing},
year={2002},
volume={E85-C},
number={3},
pages={621-624},
abstract={We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - 50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing
T2 - IEICE TRANSACTIONS on Electronics
SP - 621
EP - 624
AU - Lizhen ZHENG
AU - Xiaofan MENG
AU - Stephen WHITELEY
AU - Theodore Van DUZER
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2002
AB - We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.
ER -