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This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm2) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm2, which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.
Yuya NISHIO
Nagoya University
Atsuki KOBAYASHI
Nagoya University
Kiichi NIITSU
Nagoya University
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Yuya NISHIO, Atsuki KOBAYASHI, Kiichi NIITSU, "Design and Calibration of a Small-Footprint, Low-Frequency, and Low-Power Gate Leakage Timer Using Differential Leakage Technique" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 4, pp. 269-275, April 2019, doi: 10.1587/transele.2018CDP0005.
Abstract: This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm2) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm2, which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018CDP0005/_p
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@ARTICLE{e102-c_4_269,
author={Yuya NISHIO, Atsuki KOBAYASHI, Kiichi NIITSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Calibration of a Small-Footprint, Low-Frequency, and Low-Power Gate Leakage Timer Using Differential Leakage Technique},
year={2019},
volume={E102-C},
number={4},
pages={269-275},
abstract={This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm2) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm2, which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.},
keywords={},
doi={10.1587/transele.2018CDP0005},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Design and Calibration of a Small-Footprint, Low-Frequency, and Low-Power Gate Leakage Timer Using Differential Leakage Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 269
EP - 275
AU - Yuya NISHIO
AU - Atsuki KOBAYASHI
AU - Kiichi NIITSU
PY - 2019
DO - 10.1587/transele.2018CDP0005
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2019
AB - This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm2) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm2, which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.
ER -