This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.
Tatsuya KOBAYASHI
Shizuoka University
Keita YASUTOMI
Shizuoka University
Naoki TAKADA
Shizuoka University
Shoji KAWAHITO
Shizuoka University
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Tatsuya KOBAYASHI, Keita YASUTOMI, Naoki TAKADA, Shoji KAWAHITO, "An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 538-545, October 2023, doi: 10.1587/transele.2022CTP0003.
Abstract: This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTP0003/_p
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@ARTICLE{e106-c_10_538,
author={Tatsuya KOBAYASHI, Keita YASUTOMI, Naoki TAKADA, Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast},
year={2023},
volume={E106-C},
number={10},
pages={538-545},
abstract={This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.},
keywords={},
doi={10.1587/transele.2022CTP0003},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast
T2 - IEICE TRANSACTIONS on Electronics
SP - 538
EP - 545
AU - Tatsuya KOBAYASHI
AU - Keita YASUTOMI
AU - Naoki TAKADA
AU - Shoji KAWAHITO
PY - 2023
DO - 10.1587/transele.2022CTP0003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.
ER -