The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.
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Hiroki SHIMANO, Fukashi MORISHITA, Katsumi DOSAKA, Kazutami ARIMOTO, "On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 3, pp. 356-363, March 2009, doi: 10.1587/transele.E92.C.356.
Abstract: The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.356/_p
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@ARTICLE{e92-c_3_356,
author={Hiroki SHIMANO, Fukashi MORISHITA, Katsumi DOSAKA, Kazutami ARIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform},
year={2009},
volume={E92-C},
number={3},
pages={356-363},
abstract={The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.},
keywords={},
doi={10.1587/transele.E92.C.356},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
T2 - IEICE TRANSACTIONS on Electronics
SP - 356
EP - 363
AU - Hiroki SHIMANO
AU - Fukashi MORISHITA
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
PY - 2009
DO - 10.1587/transele.E92.C.356
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2009
AB - The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.
ER -