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High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving

Naoya ONIZAWA, Takahiro HANYU, Vincent C. GAUDET

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Summary :

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

Publication
IEICE TRANSACTIONS on Electronics Vol.E92-C No.6 pp.867-874
Publication Date
2009/06/01
Publicized
Online ISSN
1745-1353
DOI
10.1587/transele.E92.C.867
Type of Manuscript
PAPER
Category
Electronic Circuits

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