We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.
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Yasuhide KURAMOCHI, Masayuki KAWABATA, Kouichiro UEKUSA, Akira MATSUZAWA, "A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 11, pp. 1630-1637, November 2010, doi: 10.1587/transele.E93.C.1630.
Abstract: We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1630/_p
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@ARTICLE{e93-c_11_1630,
author={Yasuhide KURAMOCHI, Masayuki KAWABATA, Kouichiro UEKUSA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC},
year={2010},
volume={E93-C},
number={11},
pages={1630-1637},
abstract={We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.},
keywords={},
doi={10.1587/transele.E93.C.1630},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 1630
EP - 1637
AU - Yasuhide KURAMOCHI
AU - Masayuki KAWABATA
AU - Kouichiro UEKUSA
AU - Akira MATSUZAWA
PY - 2010
DO - 10.1587/transele.E93.C.1630
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2010
AB - We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.
ER -