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A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC

Yasuhide KURAMOCHI, Masayuki KAWABATA, Kouichiro UEKUSA, Akira MATSUZAWA

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Summary :

We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

Publication
IEICE TRANSACTIONS on Electronics Vol.E93-C No.11 pp.1630-1637
Publication Date
2010/11/01
Publicized
Online ISSN
1745-1353
DOI
10.1587/transele.E93.C.1630
Type of Manuscript
PAPER
Category
Electronic Circuits

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