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A New Single-Clock Flip-Flop for Half-Swing Clocking

Young-Su KWON, In-Cheol PARK, Chong-Min KYUNG

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Summary :

A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2521-2526
Publication Date
1999/11/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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