A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.
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Young-Su KWON, In-Cheol PARK, Chong-Min KYUNG, "A New Single-Clock Flip-Flop for Half-Swing Clocking" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2521-2526, November 1999, doi: .
Abstract: A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2521/_p
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@ARTICLE{e82-a_11_2521,
author={Young-Su KWON, In-Cheol PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Single-Clock Flip-Flop for Half-Swing Clocking},
year={1999},
volume={E82-A},
number={11},
pages={2521-2526},
abstract={A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A New Single-Clock Flip-Flop for Half-Swing Clocking
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2521
EP - 2526
AU - Young-Su KWON
AU - In-Cheol PARK
AU - Chong-Min KYUNG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.
ER -