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Low-Power Architectures for Programmable Multimedia Processors

Takao NISHITANI

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Summary :

This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.2 pp.184-196
Publication Date
1999/02/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section INVITED PAPER (Special Section on VLSI for Digital Signal Processing)
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