This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.
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Takao NISHITANI, "Low-Power Architectures for Programmable Multimedia Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 184-196, February 1999, doi: .
Abstract: This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_184/_p
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@ARTICLE{e82-a_2_184,
author={Takao NISHITANI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low-Power Architectures for Programmable Multimedia Processors},
year={1999},
volume={E82-A},
number={2},
pages={184-196},
abstract={This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Low-Power Architectures for Programmable Multimedia Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 184
EP - 196
AU - Takao NISHITANI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
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JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.
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