The search functionality is under construction.
The search functionality is under construction.

PLL Frequency Synthesizer with Multi-Phase Detector

Yasuaki SUMI, Kouichi SYOUBU, Shigeki OBOTE, Yutaka FUKUI, Yoshio ITOH

  • Full Text Views

    0

  • Cite this

Summary :

The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.3 pp.431-435
Publication Date
1999/03/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category

Authors

Keyword