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A semi-synchronous circuit is a circuit in which the clock is assumed to be distributed periodically to each individual register, though not necessarily to all registers simultaneously. In this paper, we propose an algorithm to achieve the target clock period by modifying a given target clock schedule as small as possible, where the realization cost of the target clock schedule is assumed to be minimum. The proposed algorithm iteratively improves a feasible clock schedule. The algorithm finds a set of registers that can reduce the cost by changing their clock timings with same amount, and changes the clock timing with optimal amount. Experiments show that the algorithm achieves the target clock period with fewer modifications.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2552-2557

- Publication Date
- 2000/12/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category
- Performance Optimization

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Tomoyuki YODA, Atsushi TAKAHASHI, "Clock Schedule Design for Minimum Realization Cost" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2552-2557, December 2000, doi: .

Abstract: A semi-synchronous circuit is a circuit in which the clock is assumed to be distributed periodically to each individual register, though not necessarily to all registers simultaneously. In this paper, we propose an algorithm to achieve the target clock period by modifying a given target clock schedule as small as possible, where the realization cost of the target clock schedule is assumed to be minimum. The proposed algorithm iteratively improves a feasible clock schedule. The algorithm finds a set of registers that can reduce the cost by changing their clock timings with same amount, and changes the clock timing with optimal amount. Experiments show that the algorithm achieves the target clock period with fewer modifications.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2552/_p

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@ARTICLE{e83-a_12_2552,

author={Tomoyuki YODA, Atsushi TAKAHASHI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Clock Schedule Design for Minimum Realization Cost},

year={2000},

volume={E83-A},

number={12},

pages={2552-2557},

abstract={A semi-synchronous circuit is a circuit in which the clock is assumed to be distributed periodically to each individual register, though not necessarily to all registers simultaneously. In this paper, we propose an algorithm to achieve the target clock period by modifying a given target clock schedule as small as possible, where the realization cost of the target clock schedule is assumed to be minimum. The proposed algorithm iteratively improves a feasible clock schedule. The algorithm finds a set of registers that can reduce the cost by changing their clock timings with same amount, and changes the clock timing with optimal amount. Experiments show that the algorithm achieves the target clock period with fewer modifications.},

keywords={},

doi={},

ISSN={},

month={December},}

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TY - JOUR

TI - Clock Schedule Design for Minimum Realization Cost

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2552

EP - 2557

AU - Tomoyuki YODA

AU - Atsushi TAKAHASHI

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2000

AB - A semi-synchronous circuit is a circuit in which the clock is assumed to be distributed periodically to each individual register, though not necessarily to all registers simultaneously. In this paper, we propose an algorithm to achieve the target clock period by modifying a given target clock schedule as small as possible, where the realization cost of the target clock schedule is assumed to be minimum. The proposed algorithm iteratively improves a feasible clock schedule. The algorithm finds a set of registers that can reduce the cost by changing their clock timings with same amount, and changes the clock timing with optimal amount. Experiments show that the algorithm achieves the target clock period with fewer modifications.

ER -