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This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2569-2576

- Publication Date
- 2000/12/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category
- Layout Synthesis

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Jun'ichiro MINAMI, Tetsushi KOIDE, Shin'ichi WAKABAYASHI, "An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2569-2576, December 2000, doi: .

Abstract: This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2569/_p

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@ARTICLE{e83-a_12_2569,

author={Jun'ichiro MINAMI, Tetsushi KOIDE, Shin'ichi WAKABAYASHI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints},

year={2000},

volume={E83-A},

number={12},

pages={2569-2576},

abstract={This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.},

keywords={},

doi={},

ISSN={},

month={December},}

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TY - JOUR

TI - An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2569

EP - 2576

AU - Jun'ichiro MINAMI

AU - Tetsushi KOIDE

AU - Shin'ichi WAKABAYASHI

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2000

AB - This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

ER -