The search functionality is under construction.
The search functionality is under construction.

An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints

Jun'ichiro MINAMI, Tetsushi KOIDE, Shin'ichi WAKABAYASHI

  • Full Text Views

    0

  • Cite this

Summary :

This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2569-2576
Publication Date
2000/12/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Layout Synthesis

Authors

Keyword