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Another high performance simulated annealing is proposed which we call widely stepping simulated annealing (WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (*dE*_{c}) at the critical temperature. The WSSA uses a function (*H*(*t*)) that represents the probability for a hill-climbing with the *dE*_{c} of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature *t*. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2584-2591

- Publication Date
- 2000/12/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category
- Layout Synthesis

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Shunji SAIKA, Masahiro FUKUI, Masahiko TOYONAGA, Toshiro AKINO, "WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2584-2591, December 2000, doi: .

Abstract: Another high performance simulated annealing is proposed which we call widely stepping simulated annealing (WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (*dE*_{c}) at the critical temperature. The WSSA uses a function (*H*(*t*)) that represents the probability for a hill-climbing with the *dE*_{c} of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature *t*. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2584/_p

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@ARTICLE{e83-a_12_2584,

author={Shunji SAIKA, Masahiro FUKUI, Masahiko TOYONAGA, Toshiro AKINO, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement},

year={2000},

volume={E83-A},

number={12},

pages={2584-2591},

abstract={Another high performance simulated annealing is proposed which we call widely stepping simulated annealing (WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (*dE*_{c}) at the critical temperature. The WSSA uses a function (*H*(*t*)) that represents the probability for a hill-climbing with the *dE*_{c} of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature *t*. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.},

keywords={},

doi={},

ISSN={},

month={December},}

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TY - JOUR

TI - WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2584

EP - 2591

AU - Shunji SAIKA

AU - Masahiro FUKUI

AU - Masahiko TOYONAGA

AU - Toshiro AKINO

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2000

AB - Another high performance simulated annealing is proposed which we call widely stepping simulated annealing (WSSA). It flies from a starting high temperature to a finishing low temperature staying at only twenty or so temperatures to approach thermal equilibriums. We survey the phase transition in simulated annealing process and estimate the major cost variation (*dE*_{c}) at the critical temperature. The WSSA uses a function (*H*(*t*)) that represents the probability for a hill-climbing with the *dE*_{c} of cost increase to be accepted in Metropolis' Monte Carlo simulation at temperature *t*. We have applied the first version of WSSA to one dimensional transistor placement optimizations for several industrial standard cells, and compared its performance with simulated annealing with a geometrically scheduled cooling. The solutions by the WSSA are as good as, and sometimes much better than, the solutions by the simulated annealing, while the time consumption by the WSSA is properly under one 30th of that by the simulated annealing.

ER -