The search functionality is under construction.

The search functionality is under construction.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field *GF*(2^{m}). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing *AB*^{2} multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (*m*+1)(*T*_{AND}+*T*_{XOR}). The second proposed structure is a modification of the first structure, and it requires (*m*+2) *T*_{XOR} delays. Moreover, the proposed multipliers can perform *A*^{2i}*B*^{2j} computations by shuffling the coefficients to make *i* and *j* integers. For the computing multiplication in *GF*(2^{m}), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2657-2663

- Publication Date
- 2000/12/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- VLSI Design Technology and CAD

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

Copy

Chung-Hsin LIU, Nen-Fu HUANG, Chiou-Yng LEE, "Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2657-2663, December 2000, doi: .

Abstract: This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field *GF*(2^{m}). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing *AB*^{2} multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (*m*+1)(*T*_{AND}+*T*_{XOR}). The second proposed structure is a modification of the first structure, and it requires (*m*+2) *T*_{XOR} delays. Moreover, the proposed multipliers can perform *A*^{2i}*B*^{2j} computations by shuffling the coefficients to make *i* and *j* integers. For the computing multiplication in *GF*(2^{m}), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2657/_p

Copy

@ARTICLE{e83-a_12_2657,

author={Chung-Hsin LIU, Nen-Fu HUANG, Chiou-Yng LEE, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture},

year={2000},

volume={E83-A},

number={12},

pages={2657-2663},

abstract={This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field *GF*(2^{m}). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing *AB*^{2} multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (*m*+1)(*T*_{AND}+*T*_{XOR}). The second proposed structure is a modification of the first structure, and it requires (*m*+2) *T*_{XOR} delays. Moreover, the proposed multipliers can perform *A*^{2i}*B*^{2j} computations by shuffling the coefficients to make *i* and *j* integers. For the computing multiplication in *GF*(2^{m}), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.},

keywords={},

doi={},

ISSN={},

month={December},}

Copy

TY - JOUR

TI - Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2657

EP - 2663

AU - Chung-Hsin LIU

AU - Nen-Fu HUANG

AU - Chiou-Yng LEE

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2000

AB - This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field *GF*(2^{m}). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing *AB*^{2} multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (*m*+1)(*T*_{AND}+*T*_{XOR}). The second proposed structure is a modification of the first structure, and it requires (*m*+2) *T*_{XOR} delays. Moreover, the proposed multipliers can perform *A*^{2i}*B*^{2j} computations by shuffling the coefficients to make *i* and *j* integers. For the computing multiplication in *GF*(2^{m}), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

ER -