The search functionality is under construction.

The search functionality is under construction.

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.1 pp.128-138

- Publication Date
- 2000/01/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- VLSI Design Technology and CAD

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

Copy

Jyh-Herng WANG, "Current Waveform Simulation for CMOS VLSI Circuits Considering Event-Overlapping" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 1, pp. 128-138, January 2000, doi: .

Abstract: Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_1_128/_p

Copy

@ARTICLE{e83-a_1_128,

author={Jyh-Herng WANG, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Current Waveform Simulation for CMOS VLSI Circuits Considering Event-Overlapping},

year={2000},

volume={E83-A},

number={1},

pages={128-138},

abstract={Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.},

keywords={},

doi={},

ISSN={},

month={January},}

Copy

TY - JOUR

TI - Current Waveform Simulation for CMOS VLSI Circuits Considering Event-Overlapping

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 128

EP - 138

AU - Jyh-Herng WANG

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 1

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - January 2000

AB - Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

ER -