The search functionality is under construction.
The search functionality is under construction.

A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files

Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI

  • Full Text Views

    0

  • Cite this

Summary :

In digital signal processing, bit width of intermediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files, one of which is used by input and output variables and the other one is used by intermediate variables. This paper proposes a hardware/software cosynthesis system for digital signal processor cores with two types of register files. Given an application program and its data, the system synthesizes a hardware description of a processor core, an object code running on the processor core, and software environments. A synthesized processor core can be composed of a processor kernel, multiple data memory buses, hardware loop units, addressing units, and multiple functional units. Furthermore it can have two types of register files RF1 and RF2. The bit width and number of registers in RF1 or RF2 will be determined based on a given application program. Thus a synthesized processor core will have small area with keeping high precision of intermediate operations compared with a processor core with only one register file. The experimental results demonstrate the effectiveness of the proposed system.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.3 pp.442-451
Publication Date
2000/03/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category

Authors

Keyword