This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Jun-Young PARK, Jin-Ku KANG, "A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1100-1105, June 2000, doi: .
Abstract: This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1100/_p
Copy
@ARTICLE{e83-a_6_1100,
author={Jun-Young PARK, Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method},
year={2000},
volume={E83-A},
number={6},
pages={1100-1105},
abstract={This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1100
EP - 1105
AU - Jun-Young PARK
AU - Jin-Ku KANG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
ER -