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As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.6 pp.1115-1122

- Publication Date
- 2000/06/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))

- Category

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

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Kwang-Ki RYOO, Hyunchul SHIN, Jong-Wha CHONG, "A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1115-1122, June 2000, doi: .

Abstract: As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1115/_p

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@ARTICLE{e83-a_6_1115,

author={Kwang-Ki RYOO, Hyunchul SHIN, Jong-Wha CHONG, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design},

year={2000},

volume={E83-A},

number={6},

pages={1115-1122},

abstract={As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.},

keywords={},

doi={},

ISSN={},

month={June},}

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TY - JOUR

TI - A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1115

EP - 1122

AU - Kwang-Ki RYOO

AU - Hyunchul SHIN

AU - Jong-Wha CHONG

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 6

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - June 2000

AB - As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.

ER -