A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Tetsuro ITAKURA, Tetsuya IIDA, "A Simple Phase Compensation Technique with Improved PSRR for CMOS Opamps" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 941-948, June 2000, doi: .
Abstract: A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_941/_p
Copy
@ARTICLE{e83-a_6_941,
author={Tetsuro ITAKURA, Tetsuya IIDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Simple Phase Compensation Technique with Improved PSRR for CMOS Opamps},
year={2000},
volume={E83-A},
number={6},
pages={941-948},
abstract={A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A Simple Phase Compensation Technique with Improved PSRR for CMOS Opamps
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 941
EP - 948
AU - Tetsuro ITAKURA
AU - Tetsuya IIDA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17
ER -