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The interconnect analysis of on- and off-chips is very important in the design of high-speed signal processing, digital communication, and microwave electronic systems. When the interconnects are characterized by sampled data via electromagnetic analysis, the circuit-level simulation of the network requires rational approximation of the sampled data. Since the frequency band of the sampled data is more than 10 GHz, the rational function must fit into it at many frequency points. The rational function is approximated using the orthogonal least-squares method. With an increase in the number of the fitting data, the least-squares method suffers from a singularity problem. To avoid this, the sampled data are hierarchically approximated in this paper. Moreover, to reduce the computational cost of the circuit-level simulation, the parameter matrix of the interconnects is approximated by a rational matrix with one common denominator polynomial, and the selective orthogonalization procedure is presented.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.9 pp.1833-1843

- Publication Date
- 2000/09/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- General Fundamentals and Boundaries

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Yuichi TANJI, Mamoru TANAKA, "Hierarchical Least-Squares Algorithm for Macromodeling High-Speed Interconnects Characterized by Sampled Data" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 9, pp. 1833-1843, September 2000, doi: .

Abstract: The interconnect analysis of on- and off-chips is very important in the design of high-speed signal processing, digital communication, and microwave electronic systems. When the interconnects are characterized by sampled data via electromagnetic analysis, the circuit-level simulation of the network requires rational approximation of the sampled data. Since the frequency band of the sampled data is more than 10 GHz, the rational function must fit into it at many frequency points. The rational function is approximated using the orthogonal least-squares method. With an increase in the number of the fitting data, the least-squares method suffers from a singularity problem. To avoid this, the sampled data are hierarchically approximated in this paper. Moreover, to reduce the computational cost of the circuit-level simulation, the parameter matrix of the interconnects is approximated by a rational matrix with one common denominator polynomial, and the selective orthogonalization procedure is presented.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_9_1833/_p

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@ARTICLE{e83-a_9_1833,

author={Yuichi TANJI, Mamoru TANAKA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Hierarchical Least-Squares Algorithm for Macromodeling High-Speed Interconnects Characterized by Sampled Data},

year={2000},

volume={E83-A},

number={9},

pages={1833-1843},

abstract={The interconnect analysis of on- and off-chips is very important in the design of high-speed signal processing, digital communication, and microwave electronic systems. When the interconnects are characterized by sampled data via electromagnetic analysis, the circuit-level simulation of the network requires rational approximation of the sampled data. Since the frequency band of the sampled data is more than 10 GHz, the rational function must fit into it at many frequency points. The rational function is approximated using the orthogonal least-squares method. With an increase in the number of the fitting data, the least-squares method suffers from a singularity problem. To avoid this, the sampled data are hierarchically approximated in this paper. Moreover, to reduce the computational cost of the circuit-level simulation, the parameter matrix of the interconnects is approximated by a rational matrix with one common denominator polynomial, and the selective orthogonalization procedure is presented.},

keywords={},

doi={},

ISSN={},

month={September},}

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TY - JOUR

TI - Hierarchical Least-Squares Algorithm for Macromodeling High-Speed Interconnects Characterized by Sampled Data

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1833

EP - 1843

AU - Yuichi TANJI

AU - Mamoru TANAKA

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 9

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - September 2000

AB - The interconnect analysis of on- and off-chips is very important in the design of high-speed signal processing, digital communication, and microwave electronic systems. When the interconnects are characterized by sampled data via electromagnetic analysis, the circuit-level simulation of the network requires rational approximation of the sampled data. Since the frequency band of the sampled data is more than 10 GHz, the rational function must fit into it at many frequency points. The rational function is approximated using the orthogonal least-squares method. With an increase in the number of the fitting data, the least-squares method suffers from a singularity problem. To avoid this, the sampled data are hierarchically approximated in this paper. Moreover, to reduce the computational cost of the circuit-level simulation, the parameter matrix of the interconnects is approximated by a rational matrix with one common denominator polynomial, and the selective orthogonalization procedure is presented.

ER -