We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.
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Ankur SRIVASTAVA, Chunhong CHEN, Majid SARRAFZADEH, "Timing Driven Gate Duplication in Technology Independent Phase" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2673-2680, November 2001, doi: .
Abstract: We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2673/_p
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@ARTICLE{e84-a_11_2673,
author={Ankur SRIVASTAVA, Chunhong CHEN, Majid SARRAFZADEH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Timing Driven Gate Duplication in Technology Independent Phase},
year={2001},
volume={E84-A},
number={11},
pages={2673-2680},
abstract={We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Timing Driven Gate Duplication in Technology Independent Phase
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2673
EP - 2680
AU - Ankur SRIVASTAVA
AU - Chunhong CHEN
AU - Majid SARRAFZADEH
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.
ER -