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Timing Driven Gate Duplication in Technology Independent Phase

Ankur SRIVASTAVA, Chunhong CHEN, Majid SARRAFZADEH

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Summary :

We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2673-2680
Publication Date
2001/11/01
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Logic Synthesis

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